Siwan Dong

19 papers Journal 18Unranked 1
YearRankTypeTitle / Venue / Authors
2026 J jnl
A 32Gb/s 0.63ps jitter half-rate CDR with ultra-fine interval multi-phase clock sampling and dual-path feedback DCO.
Microelectron. J.
Siwan Dong, Shenzhu Wu, Xiaoliang Ji, Jinfu Wang, Xiaohui Li, Junwei Zhu
2026 J jnl
An 8-Bit 160-MS/s Charge Injection SAR ADC With Build-in Offset Calibration for Computing-in-Memory Macros.
IEEE Trans. Circuits Syst. II Express Briefs
Siwan Dong, Jingyu Wang
2025 J jnl
A small area-occupation three-stage OTA with transistor resistance and parasitic capacitance Q-factor modulation for miniaturized communication systems.
Microelectron. J.
Yangtao Hu, Siwan Dong, Xiaoliang Ji, Zengwei Qi, Cheng Shan
2024 J jnl
A 0.6V 119 dB High-CMRR Low-NEF PGA with common-mode voltage control for ECG recording.
Microelectron. J.
Siwan Dong, Ruoyu Zhang, Chuqiang Jing, Menghan Yuan
2024 J jnl
An 11.36-Bit 405 μW SAR-VCO ADC with single-path differential VCO-based quantizer in 65 nm CMOS.
Microelectron. J.
Siwan Dong, Menghan Yuan, Sihao Ning
2023 J jnl
A 0.6-1.8 V/0.4-1.6 V Input/Output LDO with High PSRR over 50 dB/30 dB in Dual-Modes.
Circuits Syst. Signal Process.
Siwan Dong, Sen Bu, Xingyuan Tong
2023 J jnl
A Bi/Tri-level Self-Adaptive Two-Step DAC Switching Scheme for High-Power Efficiency SAR-Based ADCs.
Circuits Syst. Signal Process.
Siwan Dong, Changxiang Liu, Sen Bu, Jiaqi Li
2023 — conf
A sharpened reconfigurable CIC filter for multi-channel human-computer interaction data sampling.
AIPR
Siwan Dong, Peng Wang, Sihao Ning, Wenju Yang
2022 J jnl
A 0.6-V 12-bit 13.2-fJ/conversion-step SAR ADC with time-domain VCDL-based comparator and metastability immunity technique.
Microelectron. J.
Xingyuan Tong, Wei Jin, Chunming Zhang, Xin Xin, Siwan Dong, Qinqin Li
2022 J jnl
A 0.6-V, 1.56-nW, 5.87-ppm/°C, 0.23%/V CMOS-Only Subthreshold Voltage Reference with the Threshold Voltage Difference.
Circuits Syst. Signal Process.
Xin Xin, Yuanhao Hu, Jueping Cai, Siwan Dong, Xingyuan Tong
2021 J jnl
A 0.3-V 8.72-nW OTA with Bulk-Driven Low-Impedance Compensation for Ultra-Low Power Applications.
Circuits Syst. Signal Process.
Siwan Dong, Yu Wang, Xingyuan Tong, Yarong Wang, Cong Liu
2021 J jnl
A chaos-based true random number generator based on OTA sharing and non-flipped folded Bernoulli mapping for high-precision ADC calibration.
Microelectron. J.
Siwan Dong, Yarong Wang, Xin Xin, Xingyuan Tong
2021 J jnl
A three-stage OTA with hybrid active miller enhanced compensation technique for large to heavy load applications.
Microelectron. J.
Siwan Dong, Cong Liu, Xin Xin, Xingyuan Tong
2020 J jnl
A 17.6-nW 35.7-ppm/°C Temperature Coefficient All-SVT-MOSFET Subthreshold Voltage Reference in Standard 0.18-μm N-Well CMOS.
IEEE Access
Xingyuan Tong, Andi Yang, Siwan Dong
2019 J jnl
A 10-Bit 120 kS/s SAR ADC Without Reset Energy for Biomedical Electronics.
Circuits Syst. Signal Process.
Xingyuan Tong, Mengdi Song, Yawen Chen, Siwan Dong
2018 J jnl
A transconductance-enhancement cascode Miller compensation for low-power multistage amplifiers.
Microelectron. J.
Siwan Dong, Zhangming Zhu
2018 J jnl
Proactive correction coset decoding scheme based on SEC-DED code for multibit asymmetric errors in STT-MRAM.
Microelectron. J.
Liwen Liu, Yiqi Zhuang, Li Zhang, Hualian Tang, Siwan Dong
2015 J jnl
A High Linear CMOS Body Effect Compensation Bootstrapped Switch.
J. Circuits Syst. Comput.
Siwan Dong, Minjie Liu, Zhangming Zhu, Yintang Yang
2015 J jnl
A low-jitter wide-range duty cycle corrector for high-speed high-precision ADC.
Microelectron. J.
Minjie Liu, Yingzi Jiang, Siwan Dong, Zhangming Zhu, Yintang Yang