Siva Satyendra Sahoo

38 papers A* 3A 4C 3Misc 5Journal 13Unranked 9
YearRankTypeTitle / Venue / Authors
2025 — conf
Approximate Arithmetic Circuits Enabling Energy-Efficient Edge Computing.
MOCAST
Salim Ullah, Siva Satyendra Sahoo, Akash Kumar
2025 J jnl
AxOSyn: An Open-source Framework for Synthesizing Novel Approximate Arithmetic Operators.
CoRR
Siva Satyendra Sahoo, Salim Ullah, Akash Kumar
2025 Misc conf
Design, Model, and Explore Approximate Arithmetic Operators with AI/ML: A Tutorial.
CASES
Salim Ullah, Siva Satyendra Sahoo, Akash Kumar
2025 J jnl
EMGAxO: Extending Machine Learning Hardware Generators With Approximate Operators.
IEEE Embed. Syst. Lett.
Ali Asghar, Shahzad Bangash, Suleman Shah, Laiq Hasan, Salim Ullah, Siva Satyendra Sahoo, Akash Kumar
2025 A conf
Invited Paper: Circuit and Architecture Design with Emerging Computing Paradigms.
ICCAD
Salim Ullah, Siva Satyendra Sahoo, Can Li, Chao Li, Liu Liu, Tomas Sousa Pereira, Bo Wen, Xunzhao Yin, Armin Darjani, Nima Kavand, Chakravarthy Bodla, Rupa Yashaswi Panduga, Aniruddh Holemadlu, Johannes Maly, Jonathan Förste, Samarth Vadia, Xiaobo Sharon Hu, Akash Kumar
2025 Misc conf
Special Sessions - Emerging Scope and Design Challenges for Approximate Computing: Optimizing Accuracy-PPA trade-offs and Beyond.
CASES
Siva Satyendra Sahoo, Bastien Deveautour, Marcello Traiola, Chongyan Gu, Yun Wu, Aditya Japa, Salim Ullah, Akash Kumar
2025 — conf
SpiRec: Soft-Logic Architecture Exploration of Reconfigurable Systems for Spiking Neural Networks.
ASAP
Xunqin Lai, Federico Corradi, Siva Satyendra Sahoo
2024 J jnl
AxOCS: Scaling FPGA-Based Approximate Operators Using Configuration Supersampling.
IEEE Trans. Circuits Syst. I Regul. Pap.
Siva Satyendra Sahoo, Salim Ullah, Soumyo Bhattacharjee, Akash Kumar
2024 J jnl
AxOSpike: Spiking Neural Networks-Driven Approximate Operator Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Salim Ullah, Siva Satyendra Sahoo, Akash Kumar
2024 — ch.
Designing Resource-Efficient Hardware Arithmetic for FPGA-Based Accelerators Leveraging Approximations and Mixed Quantizations.
Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing: Hardware Architectures
Salim Ullah, Siva Satyendra Sahoo, Akash Kumar
2024 Misc conf
Enabling Energy-efficient AI Computing: Leveraging Application-specific Approximations : (Education Class).
CASES
Salim Ullah, Siva Satyendra Sahoo, Akash Kumar
2024 — conf
On-chip Memory in Accelerator-based Systems: A System Technology Co-Optimization (STCO) Perspective for Emerging Device Technologies.
SOCC
Siva Satyendra Sahoo, Dawit Burusie Abdi, Julien Ryckaert, James Myers, Dwaipayan Biswas
2023 J jnl
AxOCS: Scaling FPGA-based Approximate Operators using Configuration Supersampling.
CoRR
Siva Satyendra Sahoo, Salim Ullah, Soumyo Bhattacharjee, Akash Kumar
2023 J jnl
AxOMaP: Designing FPGA-based Approximate Arithmetic Operators using Mathematical Programming.
CoRR
Siva Satyendra Sahoo, Salim Ullah, Akash Kumar
2023 — conf
CoOAx: Correlation-aware Synthesis of FPGA-based Approximate Operators.
ACM Great Lakes Symposium on VLSI
Salim Ullah, Siva Satyendra Sahoo, Akash Kumar
2023 J jnl
NvMISC: Toward an FPGA-Based Emulation Platform for RISC-V and Nonvolatile Memories.
IEEE Embed. Syst. Lett.
Yuankang Zhao, Salim Ullah, Siva Satyendra Sahoo, Akash Kumar
2023 — conf
SyFAxO-GeN: Synthesizing FPGA-Based Approximate Operators with Generative Networks.
ASP-DAC
Rohit Ranjan, Salim Ullah, Siva Satyendra Sahoo, Akash Kumar
2022 J jnl
BOT-MICS: Bounding Time Using Analytics in Mixed-Criticality Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Behnaz Ranjbar, Ali Hosseinghorban, Siva Satyendra Sahoo, Alireza Ejlali, Akash Kumar
2022 C conf
PosAx-O: Exploring Operator-level Approximations for Posit Arithmetic in Embedded AI/ML.
DSD
Amritha Immaneni, Salim Ullah, Suresh Nambi, Siva Satyendra Sahoo, Akash Kumar
2021 J jnl
Area-Optimized Accurate and Approximate Softcore Signed Multiplier Architectures.
IEEE Trans. Computers
Salim Ullah, Hendrik Schmidl, Siva Satyendra Sahoo, Semeen Rehman, Akash Kumar
2021 A* conf
CLAppED: A Design Framework for Implementing Cross-Layer Approximation in FPGA-based Embedded Systems.
DAC
Salim Ullah, Siva Satyendra Sahoo, Akash Kumar
2021 C conf
CLEO-CoDe: Exploiting Constrained Decoding for Cross-Layer Energy Optimization in Heterogeneous Embedded Systems.
VLSI-SoC
Siva Satyendra Sahoo, Akash Kumar
2021 Misc conf
Emergent design challenges for embedded systems and paths forward: mixed-criticality, energy, reliability and security perspectives.
CODES+ISSS
Siva Satyendra Sahoo, Akash Kumar, Martin Decky, Samuel Chang Bing Wong, Geoff V. Merrett, Yinyuan Zhao, Jiachen Wang, Xiaohang Wang, Amit Kumar Singh
2021 J jnl
ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-Based Systems.
IEEE Access
Suresh Nambi, Salim Ullah, Siva Satyendra Sahoo, Aditya Lohana, Farhad Merchant, Akash Kumar
2021 A conf
Improving the Timing Behaviour of Mixed-Criticality Systems Using Chebyshev's Theorem.
DATE
Behnaz Ranjbar, Ali Hoseinghorban, Siva Satyendra Sahoo, Alireza Ejlali, Akash Kumar
2021 J jnl
ReLAccS: A Multilevel Approach to Accelerator Design for Reinforcement Learning on FPGA-Based Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Akhil Raj Baranwal, Salim Ullah, Siva Satyendra Sahoo, Akash Kumar
2021 C conf
Using Monte Carlo Tree Search for EDA - A Case-study with Designing Cross-layer Reliability for Heterogeneous Embedded Systems.
VLSI-SoC
Siva Satyendra Sahoo, Akash Kumar
2020 A* conf
CL(R)Early: An Early-stage DSE Methodology for Cross-Layer Reliability-aware Heterogeneous Embedded Systems.
DAC
Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar
2020 A conf
DiSCERN: Distilling Standard-Cells for Emerging Reconfigurable Nanotechnologies.
DATE
Shubham Rai, Michael Raitza, Siva Satyendra Sahoo, Akash Kumar
2020 J jnl
ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-based Systems.
CoRR
Suresh Nambi, Salim Ullah, Aditya Lohana, Siva Satyendra Sahoo, Farhad Merchant, Akash Kumar
2020 — conf
Markov Chain-based Modeling and Analysis of Checkpointing with Rollback Recovery for Efficient DSE in Soft Real-time Systems.
DFT
Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar
2019 A* conf
A Hybrid Agent-based Design Methodology for Dynamic Cross-layer Reliability in Heterogeneous Embedded Systems.
DAC
Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar
2019 J jnl
Multi-objective design space exploration for system partitioning of FPGA-based Dynamic Partially Reconfigurable Systems.
Integr.
Siva Satyendra Sahoo, Tuan D. A. Nguyen, Bharadwaj Veeravalli, Akash Kumar
2018 Misc conf
CLRFrame: An Analysis Framework for Designing Cross-Layer Reliability in Embedded Systems.
VLSID
Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar
2018 — conf
Lifetime-aware design methodology for dynamic partially reconfigurable systems.
ASP-DAC
Siva Satyendra Sahoo, Tuan D. A. Nguyen, Bharadwaj Veeravalli, Akash Kumar
2018 — conf
QoS-Aware Cross-Layer Reliability-Integrated FPGA-Based Dynamic Partially Reconfigurable System Partitioning.
FPT
Siva Satyendra Sahoo, Tuan D. A. Nguyen, Bharadwaj Veeravalli, Akash Kumar
2016 — conf
Cross-layer fault-tolerant design of real-time systems.
DFT
Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar
2016 A conf
Design and evaluation of reliability-oriented task re-mapping in MPSoCs using time-series analysis of intermittent faults.
DATE
Siva Satyendra Sahoo, Akash Kumar, Bharadwaj Veeravalli