Siva G. Narendra

45 papers A* 3A 8C 2Misc 2Journal 16Unranked 13

Year	Rank	Type	Title / Venue / Authors
2012	C	`conf`	Performance analysis of CNFET based circuits in the presence of fabrication imperfections. ISCAS Malgorzata Chrzanowska-Jeske, Rehman Ashraf, Rajeev K. Nain, Siva G. Narendra
2010	—	`conf`	Benefits and barriers for probabilistic design. ASP-DAC Siva G. Narendra
2010	—	`conf`	Design methodology for Carbon Nanotube based circuits in the presence of metallic tubes. NANOARCH Rehman Ashraf, Rajeev K. Nain, Malgorzata Chrzanowska-Jeske, Siva G. Narendra
2010	—	`conf`	The semiconductor industry in 2025. ISSCC Azeez Bhavnagarwala, Shekhar Borkar, Takayasu Sakurai, Siva G. Narendra
2010	—	`conf`	Yield enhancement by tube redundancy in CNFET-based circuits. ICECS Rehman Ashraf, Rajeev K. Nain, Malgorzata Chrzanowska-Jeske, Siva G. Narendra
2008	C	`conf`	Carbon nanotube circuit design choices in the presence of metallic tubes. ISCAS Rehman Ashraf, Malgorzata Chrzanowska-Jeske, Siva G. Narendra
2008	J	`jnl`	Introduction to the Special Issue on the 2007 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits David Money Harris, Sreedhar Natarajan, Ram K. Krishnamurthy, Siva G. Narendra
2008	—	`conf`	Power Systems from the Gigawatt to the Microwatt - Generation, Distribution, Storage and Efficient Use of Energy (Forum). ISSCC Eugenio Cantatore, Siva G. Narendra
2007	—	`conf`	Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging. ISSCC James W. Tschanz, Nam-Sung Kim, Saurabh Dighe, Jason Howard, Gregory Ruhl, Sriram R. Vangal, Siva G. Narendra, Yatin Hoskote, Howard Wilson, Carol Lam, Matthew Shuman, Carlos Tokunaga, Dinesh Somasekhar, Stephen Tang, David Finan, Tanay Karnik, Nitin Borkar, Nasser A. Kurd, Vivek De
2007	—	`conf`	TD: Trends in Wireless Systems. ISSCC Donhee Ham, Siva G. Narendra
2005	J	`jnl`	A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package. IEEE J. Solid State Circuits Peter Hazucha, Gerhard Schrom, Jaehong Hahn, Bradley A. Bloechel, Paul Hack, Gregory E. Dermer, Siva G. Narendra, Donald S. Gardner, Tanay Karnik, Vivek De, Shekhar Borkar
2005	—	`conf`	Adaptive circuit techniques to minimize variation impacts on microprocessor performance and power. ISCAS (1) James W. Tschanz, Siva G. Narendra, Ali Keshavarzi, Vivek De
2005	—	`conf`	Cascode buffer for monolithic voltage conversion operating at high input supply voltages. ISCAS (1) Volkan Kursun, Gerhard Schrom, Vivek De, Eby G. Friedman, Siva G. Narendra
2005	J	`jnl`	Challenges and design choices in nanoscale CMOS. ACM J. Emerg. Technol. Comput. Syst. Siva G. Narendra
2005	J	`jnl`	Monolithic voltage conversion in low-voltage CMOS technologies. Microelectron. J. Volkan Kursun, Vivek De, Eby G. Friedman, Siva G. Narendra
2004	Misc	`conf`	Design Challenges in Sub-100nm High Performance Microprocessors. VLSI Design Siva G. Narendra, Vasantha Erraguntla, James W. Tschanz, Nitin Borkar
2004	A*	`conf`	Design optimizations for microprocessors at low temperature. DAC Arman Vassighi, Ali Keshavarzi, Siva G. Narendra, Gerhard Schrom, Yibin Ye, Seri Lee, Greg Chrysler, Manoj Sachdev, Vivek De
2004	A	`conf`	Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation. ISLPED Gerhard Schrom, Peter Hazucha, Jae-Hong Hahn, Volkan Kursun, Donald S. Gardner, Siva G. Narendra, Tanay Karnik, Vivek De
2004	J	`jnl`	Full-chip subthreshold leakage power prediction and reduction techniques for sub-0.18-μm CMOS. IEEE J. Solid State Circuits Siva G. Narendra, Vivek De, Shekhar Borkar, Dimitri A. Antoniadis, Anantha P. Chandrakasan
2004	—	`conf`	High Input Voltage Step-Down DC-DC Converters for Integration in a Low Voltage CMOS Process. ISQED Volkan Kursun, Siva G. Narendra, Vivek De, Eby G. Friedman
2004	J	`jnl`	Low-voltage-swing monolithic dc-dc conversion. IEEE Trans. Circuits Syst. II Express Briefs Volkan Kursun, Siva G. Narendra, Vivek K. De, Eby G. Friedman
2004	J	`jnl`	Measurements and analysis of SER-tolerant latch in a 90-nm dual-V IEEE J. Solid State Circuits Peter Hazucha, Tanay Karnik, Steven Walstra, Bradley A. Bloechel, James W. Tschanz, Jose Maiz, Krishnamurthy Soumyanath, Gregory E. Dermer, Siva G. Narendra, Vivek De, Shekhar Borkar
2004	Misc	`conf`	The Influence of Process Variations on the Halo MOSFETs and its Implications on the Analog Circuit performance. VLSI Design K. Narasimhulu, Siva G. Narendra, V. Ramgopal Rao
2003	J	`jnl`	A TCP offload accelerator for 10 Gb/s Ethernet in 90-nm CMOS. IEEE J. Solid State Circuits Yatin Vasant Hoskote, Bradley A. Bloechel, Gregory E. Dermer, Vasantha Erraguntla, David Finan, Jason Howard, Dan Klowden, Siva G. Narendra, Greg Ruhl, James W. Tschanz, Sriram R. Vangal, Venkat Veeramachaneni, Howard Wilson, Jianping Xu, Nitin Borkar
2003	J	`jnl`	Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor. IEEE Trans. Very Large Scale Integr. Syst. Volkan Kursun, Siva G. Narendra, Vivek De, Eby G. Friedman
2003	J	`jnl`	Dynamic sleep transistor and body bias for active leakage power control of microprocessors. IEEE J. Solid State Circuits James W. Tschanz, Siva G. Narendra, Yibin Ye, Bradley A. Bloechel, Shekhar Borkar, Vivek De
2003	J	`jnl`	Effectiveness of adaptive supply voltage and body bias for reducing impact of parameter variations in low power and high performance microprocessors. IEEE J. Solid State Circuits James W. Tschanz, Siva G. Narendra, Raj Nair, Vivek De
2003	J	`jnl`	Forward body bias for microprocessors in 130-nm technology generation and beyond. IEEE J. Solid State Circuits Siva G. Narendra, Ali Keshavarzi, Bradley A. Bloechel, Shekhar Borkar, Vivek De
2003	—	`conf`	Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS process. CICC Peter Hazucha, Tanay Kamik, Steven Walstra, Bradley A. Bloechel, James W. Tschanz, Jose Maiz, Krishnamurthy Soumyanath, Greg Dermer, Siva G. Narendra, Vivek De, Shekhar Borkar
2003	—	`conf`	Monolithic DC-DC Converter Analysis And Mosfet Gate Voltage Optimization. ISQED Volkan Kursun, Siva G. Narendra, Vivek De, Eby G. Friedman
2003	A*	`conf`	Parameter variations and impact on circuits and microarchitecture. DAC Shekhar Borkar, Tanay Karnik, Siva G. Narendra, James W. Tschanz, Ali Keshavarzi, Vivek De
2003	A	`conf`	Temperature and process invariant MOS-based reference current generation circuits for sub-1V operation. ISLPED Stephen Tang, Siva G. Narendra, Vivek De
2002	J	`jnl`	5-GHz 32-bit integer execution core in 130-nm dual-V IEEE J. Solid State Circuits Sriram R. Vangal, Mark A. Anders, Nitin Borkar, Erik Seligman, Venkatesh Govindarajulu, Vasantha Erraguntla, Howard Wilson, Amaresh Pangal, Venkat Veeramachaneni, James W. Tschanz, Yibin Ye, Dinesh Somasekhar, Bradley A. Bloechel, Gregory E. Dermer, Ram K. Krishnamurthy, Krishnamurthy Soumyanath, Sanu Mathew, Siva G. Narendra, Mircea R. Stan, Scott Thompson, Vivek De, Shekhar Borkar
2002	J	`jnl`	Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage. IEEE J. Solid State Circuits James W. Tschanz, James T. Kao, Siva G. Narendra, Raj Nair, Dimitri A. Antoniadis, Anantha P. Chandrakasan, Vivek De
2002	J	`jnl`	Analysis of dual-V IEEE Trans. Very Large Scale Integr. Syst. Fatih Hamzaoglu, Yibin Ye, Ali Keshavarzi, Kevin Zhang, Siva G. Narendra, Shekhar Borkar, Mircea R. Stan, Vivek De
2002	—	`—`	Effect of Metal oxide semiconductor field-effect transistors threshold voltage variation on high-performance circuits. Siva G. Narendra
2002	—	`conf`	Evening Panel Discussion: Process Variation: Is It Too Much to Handle? ISQED Ron Wilson, Siva G. Narendra, Vivek De
2002	A	`conf`	Full-chip sub-threshold leakage power prediction model for sub-0.18 µm CMOS. ISLPED Siva G. Narendra, Vivek De, Shekhar Borkar, Dimitri A. Antoniadis, Anantha P. Chandrakasan
2002	J	`jnl`	Leakage and Process Variation Effects in Current Testing on Future CMOS Circuits. IEEE Des. Test Comput. Ali Keshavarzi, James W. Tschanz, Siva G. Narendra, Vivek De, W. Robert Daasch, Kaushik Roy, Manoj Sachdev, Charles F. Hawkins
2002	A	`conf`	Subthreshold leakage modeling and reduction techniques. ICCAD James T. Kao, Siva G. Narendra, Anantha P. Chandrakasan
2001	A	`conf`	Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors. ISLPED James W. Tschanz, Siva G. Narendra, Zhanping Chen, Shekhar Borkar, Manoj Sachdev, Vivek De
2001	A	`conf`	Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs. ISLPED Ali Keshavarzi, Sean Ma, Siva G. Narendra, Brad Bloechel, K. Mistry, Tahir Ghani, Shekhar Borkar, Vivek De
2001	A	`conf`	Scaling of stack effect and its application for leakage reduction. ISLPED Siva G. Narendra, Vivek De, Dimitri A. Antoniadis, Anantha P. Chandrakasan, Shekhar Borkar
1999	A	`conf`	Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's. ISLPED Ali Keshavarzi, Siva G. Narendra, Shekhar Borkar, Charles F. Hawkins, Kaushik Roy, Vivek De
1998	A*	`conf`	MTCMOS Hierarchical Sizing Based on Mutual Exclusive Discharge Patterns. DAC James T. Kao, Siva G. Narendra, Anantha P. Chandrakasan