Sithara Raveendran

15 papers C 2Misc 1Journal 5Unranked 7
YearRankTypeTitle / Venue / Authors
2023 — conf
Approximate Three-Operand Binary Adder for Error-Resilient Applications.
iSES
Darshan Halliyavar, Siddharth R. K., Vasantha M. H., Nithin Kumar Y. B., Sithara Raveendran
2022 C conf
On The Design Of Rationalised Bi-orthogonal Wavelet Using Reversible Logic.
ISCAS
Sithara Raveendran, Pranose J. Edavoor, Y. B. Nithin Kumar, M. H. Vasantha
2021 J jnl
Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic.
IEEE Access
Sithara Raveendran, Pranose J. Edavoor, Nithin Kumar Yernad Balachandra, M. H. Vasantha
2021 J jnl
Novel 4: 2 Approximate Compressor Designs for Multimedia and Neural Network Applications.
J. Circuits Syst. Comput.
Pranose J. Edavoor, Sithara Raveendran, Amol D. Rahulkar
2020 J jnl
An Approximate Low-Power Lifting Scheme Using Reversible Logic.
IEEE Access
Sithara Raveendran, Pranose J. Edavoor, Nithin Y. B. Kumar, M. H. Vasantha
2020 J jnl
Approximate Multiplier Design Using Novel Dual-Stage 4: 2 Compressors.
IEEE Access
Pranose J. Edavoor, Sithara Raveendran, Amol D. Rahulkar
2020 J jnl
Design and implementation of image kernels using reversible logic gates.
IET Image Process.
Sithara Raveendran, Pranose J. Edavoor, Nithin Kumar Yernad Balachandra, Vasantha Moodabettu Harishchandra
2020 — conf
Reversible Logic Implementation of Image Denoising for Grayscale Images.
MWSCAS
Sithara Raveendran, Pranose J. Edavoor, Nithin Kumar Y. B., M. H. Vasantha
2019 — conf
Design and Analysis of Energy Efficient Reversible Logic based Full Adder.
MWSCAS
Jagadeesh Pujar, Sithara Raveendran, Trilochan Panigrahi, Vasantha M. H., Nithin Kumar Y. B.
2018 C conf
Design and Implementation of Reversible Logic based RGB to Gray scale Color Space Converter.
TENCON
Sithara Raveendran, Pranose J. Edavoor, Nithin Y. B. Kumar, M. H. Vasantha
2018 — conf
FPGA Implementation of Square and Cube Architecture Using Vedic Mathematics.
iSES
Sampada Barve, Sithara Raveendran, Charudatta Korde, Trilochan Panigrahi, Nithin Y. B. Kumar, M. H. Vasantha
2017 — conf
Design and implementation of PID controller based on orthogonal wavelet filter-banks in FPGA.
ISED
Priyanandini Das, Pranose J. Edavoor, Sithara Raveendran, Sunil Rathore, Amol D. Rahulkar
2017 — conf
Implementation of adaptive image compression algorithm using varying bit-length daubechies wavelet coefficient with three-level encryption on Zynq 7000.
ISED
Pranose J. Edavoor, Sithara Raveendran, Amol D. Rahulkar
2016 Misc conf
Characterization of a Novel Low Leakage Power and Area Efficient 7T SRAM Cell.
VLSID
A. Venkatareddy, Sithara Raveendran, Kumar Y. B. Nithin, M. H. Vasantha
2016 — conf
FPGA realisation of PSNR and BPP driven Adaptive Compression and Encryption Algorithm for RGB Images.
ICCCNT
Pranose J. Edavoor, Sithara Raveendran, Arjun T. V., Sumesh K. P., Kumar Y. B. Nithin, M. H. Vasantha