Simon W. Moore

97 papers A* 12A 4B 9C 17Misc 2Journal 22Unranked 31

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	CHERI-SIMT: Implementing Capability Memory Protection in GPUs. ASPLOS (1) Matthew Naylor, Alexandre Joannou, A. Theodore Markettos, Paul Metzger, Simon W. Moore, Timothy M. Jones
2025	A*	`conf`	CHERIoT RTOS: An OS for Fine-Grained Memory-Safe Compartments on Low-Cost Embedded Devices. SOSP Saar Amar, Tony Chen, David Chisnall, Nathaniel Wesley Filardo, Ben Laurie, Hugo Lefeuvre, Kunyan Liu, Simon W. Moore, Robert Norton-Wright, Margo I. Seltzer, Yucong Tao, Robert N. M. Watson, Hongyan Xia
2025	J	`jnl`	It Is Time to Standardize Principles and Practices for Software Memory Safety. Commun. ACM Robert N. M. Watson, John Baldwin, David Chisnall, Tony Chen, Jessica Clarke, Brooks Davis, Nathaniel Wesley Filardo, Brett F. Gutstein, Graeme Jenkinson, Ben Laurie, Alfredo Mazzinghi, Simon W. Moore, Peter G. Neumann, Hamed Okhravi, Alex Richardson, Alex Rebert, Peter Sewell, Laurence Tratt, Murali Vijayaraghavan, Hugo Vincent, Konrad Witaszczyk
2024	C	`conf`	A Suite of Processors to Explore CHERI-RISC-V Micro Architecture. DSD Peter Rugg, Jonathan Woodruff, Alexandre Joannou, Simon W. Moore
2024	C	`conf`	Advanced Dynamic Scalarisation for RISC-V GPGPUs. ICCD Matthew Naylor, Alexandre Joannou, A. Theodore Markettos, Paul Metzger, Simon W. Moore, Timothy M. Jones
2024	J	`jnl`	CHERI: Hardware-Enabled C/C++ Memory Protection at Scale. IEEE Secur. Priv. Robert N. M. Watson, David Chisnall, Jessica Clarke, Brooks Davis, Nathaniel Wesley Filardo, Ben Laurie, Simon W. Moore, Peter G. Neumann, Alexander Richardson, Peter Sewell, Konrad Witaszczyk, Jonathan Woodruff
2024	—	`conf`	Cornucopia Reloaded: Load Barriers for CHERI Heap Temporal Safety. ASPLOS (2) Nathaniel Wesley Filardo, Brett F. Gutstein, Jonathan Woodruff, Jessica Clarke, Peter Rugg, Brooks Davis, Mark Johnston, Robert M. Norton, David Chisnall, Simon W. Moore, Peter G. Neumann, Robert N. M. Watson
2024	J	`jnl`	Randomized Testing of RISC-V CPUs Using Direct Instruction Injection. IEEE Des. Test Alexandre Joannou, Peter Rugg, Jonathan Woodruff, Franz A. Fuchs, Marno van der Maas, Matthew Naylor, Michael Roe, Robert N. M. Watson, Peter G. Neumann, Simon W. Moore
2024	C	`conf`	Safe Speculation for Cheri. ICCD Franz A. Fuchs, Jonathan Woodruff, Peter Rugg, Alexandre Joannou, Jessica Clarke, John Baldwin, Brooks Davis, Peter G. Neumann, Robert N. M. Watson, Simon W. Moore
2023	C	`conf`	Architectural Contracts for Safe Speculation. ICCD Franz A. Fuchs, Jonathan Woodruff, Peter Rugg, Marno van der Maas, Alexandre Joannou, Alexander Richardson, Jessica Clarke, Nathaniel Wesley Filardo, Brooks Davis, John Baldwin, Peter G. Neumann, Simon W. Moore, Robert N. M. Watson
2023	A*	`conf`	CHERIoT: Complete Memory Safety for Embedded Devices. MICRO Saar Amar, David Chisnall, Tony Chen, Nathaniel Wesley Filardo, Ben Laurie, Kunyan Liu, Robert M. Norton, Simon W. Moore, Yucong Tao, Robert N. M. Watson, Hongyan Xia
2023	J	`jnl`	How Flexible Is CXL's Memory Protection? Commun. ACM Samuel W. Stark, A. Theodore Markettos, Simon W. Moore
2023	J	`jnl`	How Flexible is CXL's Memory Protection?: Replacing a sledgehammer with a scalpel. ACM Queue Samuel W. Stark, A. Theodore Markettos, Simon W. Moore
2023	J	`jnl`	POETS: An Event-driven Approach to Dissipative Particle Dynamics: Implementing a Massively Compute-intensive Problem on a Novel Hard/Software Architecture. ACM Trans. Parallel Comput. Andrew D. Brown, Jonathan R. Beaumont, David B. Thomas, Julian C. Shillcock, Matthew Naylor, Graeme M. Bragg, Mark Vousden, Simon W. Moore, Shane T. Fleming
2023	J	`jnl`	The Arm Morello Evaluation Platform - Validating CHERI-Based Security in a High-Performance System. IEEE Micro Richard Grisenthwaite, Graeme Barnes, Robert N. M. Watson, Simon W. Moore, Peter Sewell, Jonathan Woodruff
2023	—	`conf`	Towards xBGAS on CHERI: Supporting a Secure Global Memory. IPDPS Workshops Mert Side, Brody Williams, John D. Leidel, Jonathan Woodruff, Simon W. Moore, Yong Chen
2022	J	`jnl`	CompartOS: CHERI Compartmentalization for Embedded Systems. CoRR Hesham Almatary, Michael Dodson, Jessica Clarke, Peter Rugg, Ivan Gomes, Michal Podhradsky, Peter G. Neumann, Simon W. Moore, Robert N. M. Watson
2022	—	`conf`	Non-deterministic event brokered computing. HEART Andrew Brown, Tim Todman, Wayne Luk, David B. Thomas, Mark Vousden, Graeme M. Bragg, Jonny Beaumont, Simon W. Moore, Alex Yakovlev, Ashur Rafiev
2022	J	`jnl`	Practical Distributed Implementation of Very Large Scale Petri Net Simulations. Trans. Petri Nets Other Model. Concurr. Ashur Rafiev, Jordan Morris, Fei Xia, Alex Yakovlev, Matthew Naylor, Simon W. Moore, David B. Thomas, Graeme M. Bragg, Mark Vousden, Andrew Brown
2022	J	`jnl`	Synchronization in graph analysis algorithms on the Partially Ordered Event-Triggered Systems many-core architecture. IET Comput. Digit. Tech. Ashur Rafiev, Alex Yakovlev, Ghaith Tarawneh, Matthew Naylor, Simon W. Moore, David B. Thomas, Graeme M. Bragg, Mark Vousden, Andrew D. Brown
2021	C	`conf`	General hardware multicasting for fine-grained message-passing architectures. PDP Matthew Naylor, Simon W. Moore, David B. Thomas, Jonathan R. Beaumont, Shane T. Fleming, Mark Vousden, A. Theodore Markettos, Thomas Bytheway, Andrew D. Brown
2020	A*	`conf`	Cornucopia: Temporal Safety for CHERI Heaps. SP Nathaniel Wesley Filardo, Brett F. Gutstein, Jonathan Woodruff, Sam Ainsworth, Lucian Paul-Trifu, Brooks Davis, Hongyan Xia, Edward Tomasz Napierala, Alexander Richardson, John Baldwin, David Chisnall, Jessica Clarke, Khilan Gudka, Alexandre Joannou, A. Theodore Markettos, Alfredo Mazzinghi, Robert M. Norton, Michael Roe, Peter Sewell, Stacey D. Son, Timothy M. Jones, Simon W. Moore, Peter G. Neumann, Robert N. M. Watson
2020	—	`conf`	Position Paper: Defending Direct Memory Access with CHERI Capabilities. HASP@MICRO A. Theodore Markettos, John Baldwin, Ruslan Bukin, Peter G. Neumann, Simon W. Moore, Robert N. M. Watson
2020	—	`conf`	Protecting Enclaves from Intra-Core Side-Channel Attacks through Physical Isolation. CYSARM@CCS Marno van der Maas, Simon W. Moore
2020	A*	`conf`	Rigorous engineering for hardware security: Formal modelling and proof in the CHERI design and implementation process. SP Kyndylan Nienhuis, Alexandre Joannou, Thomas Bauereiss, Anthony C. J. Fox, Michael Roe, Brian Campbell, Matthew Naylor, Robert M. Norton, Simon W. Moore, Peter G. Neumann, Ian Stark, Robert N. M. Watson, Peter Sewell
2020	—	`conf`	Termination detection for fine-grained message-passing architectures. ASAP Matthew Naylor, Simon W. Moore, Andrey Mokhov, David B. Thomas, Jonathan R. Beaumont, Shane T. Fleming, A. Theodore Markettos, Thomas Bytheway, Andrew D. Brown
2019	J	`jnl`	CHERI Concentrate: Practical Compressed Capabilities. IEEE Trans. Computers Jonathan Woodruff, Alexandre Joannou, Hongyan Xia, Anthony C. J. Fox, Robert M. Norton, David Chisnall, Brooks Davis, Khilan Gudka, Nathaniel Wesley Filardo, A. Theodore Markettos, Michael Roe, Peter G. Neumann, Robert N. M. Watson, Simon W. Moore
2019	A*	`conf`	CHERIvoke: Characterising Pointer Revocation using CHERI Capabilities for Temporal Memory Safety. MICRO Hongyan Xia, Jonathan Woodruff, Sam Ainsworth, Nathaniel Wesley Filardo, Michael Roe, Alexander Richardson, Peter Rugg, Peter G. Neumann, Simon W. Moore, Robert N. M. Watson, Timothy M. Jones
2019	A*	`conf`	CheriABI: Enforcing Valid Pointer Provenance and Minimizing Pointer Privilege in the POSIX C Run-time Environment. ASPLOS Brooks Davis, Robert N. M. Watson, Alexander Richardson, Peter G. Neumann, Simon W. Moore, John Baldwin, David Chisnall, Jessica Clarke, Nathaniel Wesley Filardo, Khilan Gudka, Alexandre Joannou, Ben Laurie, A. Theodore Markettos, J. Edward Maste, Alfredo Mazzinghi, Edward Tomasz Napierala, Robert M. Norton, Michael Roe, Peter Sewell, Stacey D. Son, Jonathan Woodruff
2019	J	`jnl`	Through computer architecture, darkly. Commun. ACM A. Theodore Markettos, Robert N. M. Watson, Simon W. Moore, Peter Sewell, Peter G. Neumann
2019	A*	`conf`	Thunderclap: Exploring Vulnerabilities in Operating System IOMMU Protection via DMA from Untrustworthy Peripherals. NDSS A. Theodore Markettos, Colin Rothwell, Brett F. Gutstein, Allison Pearce, Peter G. Neumann, Simon W. Moore, Robert N. M. Watson
2019	B	`conf`	Tinsel: A Manythread Overlay for FPGA Clusters. FPL Matthew Naylor, Simon W. Moore, David B. Thomas
2018	C	`conf`	CheriRTOS: A Capability Model for Embedded Devices. ICCD Hongyan Xia, Jonathan Woodruff, Hadrien Barral, Lawrence Esswood, Alexandre Joannou, Robert Kovacsics, David Chisnall, Michael Roe, Brooks Davis, Edward Napierala, John Baldwin, Khilan Gudka, Peter G. Neumann, Alexander Richardson, Simon W. Moore, Robert N. M. Watson
2017	A*	`conf`	CHERI JNI: Sinking the Java Security Model into the C. ASPLOS David Chisnall, Brooks Davis, Khilan Gudka, David Brazdil, Alexandre Joannou, Jonathan Woodruff, A. Theodore Markettos, J. Edward Maste, Robert M. Norton, Stacey D. Son, Michael Roe, Simon W. Moore, Peter G. Neumann, Ben Laurie, Robert N. M. Watson
2017	C	`conf`	Efficient Tagged Memory. ICCD Alexandre Joannou, Jonathan Woodruff, Robert Kovacsics, Simon W. Moore, Alex Bradbury, Hongyan Xia, Robert N. M. Watson, David Chisnall, Michael Roe, Brooks Davis, Edward Napierala, John Baldwin, Khilan Gudka, Peter G. Neumann, Alfredo Mazzinghi, Alex Richardson, Stacey D. Son, A. Theodore Markettos
2017	—	`conf`	Programming Model to Develop Supercomputer Combinatorial Solvers. ICPP Workshops Ghaith Tarawneh, Andrey Mokhov, Matthew Naylor, Alex Rast, Simon W. Moore, David B. Thomas, Alex Yakovlev, Andrew D. Brown
2016	B	`conf`	A consistency checker for memory subsystem traces. FMCAD Matthew Naylor, Simon W. Moore, Alan Mujumdar
2016	J	`jnl`	CHERI: A Hardware-Software System to Support the Principle of Least Privilege. ERCIM News Robert N. M. Watson, Simon W. Moore, Peter G. Neumann
2016	—	`conf`	Conquering the complexity mountain: Full-stack computer architecture teaching with FPGAs. EWME A. Theodore Markettos, Simon W. Moore, Brian D. Jones, Roy Spliet, Vlad A. Gavrila
2016	J	`jnl`	Fast Protection-Domain Crossing in the CHERI Capability-System Architecture. IEEE Micro Robert N. M. Watson, Robert M. Norton, Jonathan Woodruff, Simon W. Moore, Peter G. Neumann, Jonathan Anderson, David Chisnall, Brooks Davis, Ben Laurie, Michael Roe, Nirav H. Dave, Khilan Gudka, Alexandre Joannou, A. Theodore Markettos, Ed Maste, Steven J. Murdoch, Colin Rothwell, Stacey D. Son, Munraj Vadera
2015	C	`conf`	A generic synthesisable test bench. MEMOCODE Matthew Naylor, Simon W. Moore
2015	A*	`conf`	Beyond the PDP-11: Architectural Support for a Memory-Safe C Abstract Machine. ASPLOS David Chisnall, Colin Rothwell, Robert N. M. Watson, Jonathan Woodruff, Munraj Vadera, Simon W. Moore, Michael Roe, Brooks Davis, Peter G. Neumann
2015	A*	`conf`	CHERI: A Hybrid Capability-System Architecture for Scalable Software Compartmentalization. IEEE Symposium on Security and Privacy Robert N. M. Watson, Jonathan Woodruff, Peter G. Neumann, Simon W. Moore, Jonathan Anderson, David Chisnall, Nirav H. Dave, Brooks Davis, Khilan Gudka, Ben Laurie, Steven J. Murdoch, Robert M. Norton, Michael Roe, Stacey D. Son, Munraj Vadera
2014	B	`conf`	Interconnect for commodity FPGA clusters: Standardized or customized? FPL A. Theodore Markettos, Paul James Fox, Simon W. Moore, Andrew W. Moore
2014	J	`jnl`	Power Optimized Transceivers for Future Switched Networks. IEEE Trans. Very Large Scale Integr. Syst. Yury Audzevich, Philip M. Watts, Andrew West, Alan Mujumdar, Simon W. Moore, Andrew W. Moore
2014	B	`conf`	Rapid codesign of a soft vector processor and its compiler. FPL Matthew Naylor, Simon W. Moore
2014	—	`conf`	Reliably prototyping large SoCs using FPGA clusters. ReCoSoC Paul James Fox, A. Theodore Markettos, Simon W. Moore
2014	A*	`conf`	The CHERI capability model: Revisiting RISC in an age of risk. ISCA Jonathan Woodruff, Robert N. M. Watson, David Chisnall, Simon W. Moore, Jonathan Anderson, Brooks Davis, Ben Laurie, Peter G. Neumann, Robert M. Norton, Michael Roe
2013	B	`conf`	A 64-bit MIPS processor running freebsd on a portable FPGA tablet. FPL Jonathan Woodruff, A. Theodore Markettos, Simon W. Moore
2013	B	`conf`	A spiking neural network on a portable FPGA tablet. FPL Matthew Naylor, Paul James Fox, A. Theodore Markettos, Simon W. Moore
2013	J	`jnl`	Designing a Physical Locality Aware Coherence Protocol for Chip-Multiprocessors. IEEE Trans. Computers Christian Fensch, Nick Barrow-Williams, Robert D. Mullins, Simon W. Moore
2013	B	`conf`	Managing the FPGA memory wall: Custom computing or vector processing? FPL Matthew Naylor, Paul James Fox, A. Theodore Markettos, Simon W. Moore
2012	Misc	`conf`	Bluehive - A Field-Programable Custom Computing Machine for Extreme-Scale Real-Time Neural Network Simulation. FCCM Simon W. Moore, Paul James Fox, Steven J. T. Marsh, A. Theodore Markettos, Alan Mujumdar
2012	J	`jnl`	Energy Implications of Photonic Networks With Speculative Transmission. JOCN Philip M. Watts, Simon W. Moore, Andrew W. Moore
2012	C	`conf`	Mamba: A scalable communication centric multi-threaded processor architecture. ICCD Gregory A. Chadwick, Simon W. Moore
2010	J	`jnl`	Efficient Physical Embedding of Topologically Complex Information Processing Networks in Brains and Computer Circuits. PLoS Comput. Biol. Danielle S. Bassett, Daniel Greenfield, Andreas Meyer-Lindenberg, Daniel R. Weinberger, Simon W. Moore, Edward T. Bullmore
2010	B	`conf`	Proximity coherence for chip multiprocessors. PACT Nick Barrow-Williams, Christian Fensch, Simon W. Moore
2009	—	`conf`	A communication characterisation of Splash-2 and Parsec. IISWC Nick Barrow-Williams, Christian Fensch, Simon W. Moore
2009	J	`jnl`	An Energy and Performance Exploration of Network-on-Chip Architectures. IEEE Trans. Very Large Scale Integr. Syst. Arnab Banerjee, Pascal T. Wolkotte, Robert D. Mullins, Simon W. Moore, Gerard J. M. Smit
2009	A	`conf`	FPGAs with time-division multiplexed wiring: an architectural exploration and area analysis. FPGA Rosemary M. Francis, Simon W. Moore
2009	—	`conf`	Flow-aware allocation for on-chip networks. NOCS Arnab Banerjee, Simon W. Moore
2009	J	`jnl`	Implications of Electronics Technology Trends for Algorithm Design. Comput. J. Daniel Greenfield, Simon W. Moore
2009	A	`conf`	The Frequency Injection Attack on Ring-Oscillator-Based True Random Number Generators. CHES A. Theodore Markettos, Simon W. Moore
2008	—	`conf`	A Network of Time-Division Multiplexed Wiring for FPGAs. NOCS Rosemary M. Francis, Simon W. Moore, Robert Mullins
2008	—	`conf`	Exploring hard and soft networks-on-chip for FPGAs. FPT Rosemary M. Francis, Simon W. Moore
2008	B	`conf`	Fractal communication in software data dependency graphs. SPAA Daniel Greenfield, Simon W. Moore
2008	—	`conf`	Implications of Electronics Technology Trends to Algorithm Design. BCS Int. Acad. Conf. Daniel Greenfield, Simon W. Moore
2008	—	`conf`	Tamper Protection for Security Devices. BLISS Philip Christopher Paul, Simon W. Moore, Simon W.-B. Tam
2008	—	`conf`	The next resource war: computation vs. communication. SLIP Simon W. Moore, Daniel Greenfield
2007	—	`conf`	A Power and Energy Exploration of Network-on-Chip Architectures. NOCS Arnab Banerjee, Robert Mullins, Simon W. Moore
2007	—	`conf`	Demystifying Data-Driven and Pausible Clocking Schemes. ASYNC Robert Mullins, Simon W. Moore
2007	—	`conf`	Implications of Rent's Rule for NoC Design and Its Fault-Tolerance. NOCS Daniel Greenfield, Arnab Banerjee, Jeong-Gun Lee, Simon W. Moore
2006	—	`conf`	Adding question answering to an e-tutor for programming languages. SGAI Conf. (Applications) Kate Taylor, Simon W. Moore
2006	Misc	`conf`	An Asynchronous Interconnect Architecture for Device Security Enhancement. VLSI Design Simon Hollis, Simon W. Moore
2006	C	`conf`	An Asynchronous PLA with Improved Security Characteristics. DSD Petros Oikonomakos, Simon W. Moore
2006	C	`conf`	An area-efficient, pulse-based interconnect. ISCAS Simon Hollis, Simon W. Moore
2006	C	`conf`	Hardware-Software Codesign of a Vector Co-processor for Public Key Cryptography. DSD Jacques J. A. Fournier, Simon W. Moore
2006	C	`conf`	Implementing Cryptography on TFT Technology for Secure Display Applications. CARDIS Petros Oikonomakos, Jacques J. A. Fournier, Simon W. Moore
2006	—	`conf`	My Compiler Really Understands Me: An Adaptive Programming Language Tutor. AH Kate Taylor, Simon W. Moore
2006	C	`conf`	RasP: An Area-efficient, On-chip Network. ICCD Simon Hollis, Simon W. Moore
2006	—	`conf`	The design and implementation of a low-latency on-chip network. ASP-DAC Robert Mullins, Andrew West, Simon W. Moore
2005	—	`conf`	A Vector Approach to Cryptography Implementation. DRMTICS Jacques J. A. Fournier, Simon W. Moore
2005	A	`conf`	Security Evaluation Against Electromagnetic Analysis at Design Time. CHES Huiyun Li, A. Theodore Markettos, Simon W. Moore
2005	—	`conf`	Security evaluation against electromagnetic analysis at design time. HLDVT Huiyun Li, A. Theodore Markettos, Simon W. Moore
2005	—	`conf`	Self-Timed Circuitry for Global Clocking. ASYNC Scott Fairbanks, Simon W. Moore
2004	—	`conf`	Analog Micropipeline Rings for High Precision Timing. ASYNC Scott Fairbanks, Simon W. Moore
2004	A*	`conf`	Low-Latency Virtual-Channel Routers for On-Chip Networks. ISCA Robert Mullins, Andrew West, Simon W. Moore
2003	J	`jnl`	Balanced self-checking asynchronous logic for smart card applications. Microprocess. Microsystems Simon W. Moore, Ross J. Anderson, Robert Mullins, George S. Taylor, Jacques J. A. Fournier
2003	A	`conf`	Security Evaluation of Asynchronous Circuits. CHES Jacques J. A. Fournier, Simon W. Moore, Huiyun Li, Robert Mullins, George S. Taylor
2002	—	`conf`	Improving Smart Card Security Using Self-Timed Circuits. ASYNC Simon W. Moore, Robert Mullins, Paul A. Cunningham, Ross J. Anderson, George S. Taylor
2002	C	`conf`	JMA: The Java-Multithreading Architecture for Embedded Processors. ICCD Panit Watcharawitch, Simon W. Moore
2002	—	`conf`	Point to Point GALS Interconnect. ASYNC George S. Taylor, Simon W. Moore, Robert Mullins, Peter Robinson
2001	—	`conf`	Protecting Consumer Security Devices. E-smart Simon W. Moore
2000	—	`conf`	An On-Chip Dynamically Recalibrated Delay Line for Embedded Self-Timed Systems. ASYNC George S. Taylor, Simon W. Moore, Steve Wilcox, Peter Robinson
2000	C	`conf`	Self-Calibrating Clocks for Globally Asynchronous Locally Synchronous Systems. ICCD Simon W. Moore, George S. Taylor, Paul A. Cunningham, Robert D. Mullins, Peter Robinson
1998	C	`conf`	Rapid prototyping of self-timed circuits. ICCD Simon W. Moore, Peter Robinson
1995	J	`jnl`	Tagged Up/Down Sorter - A Hardware Priority Queue. Comput. J. Simon W. Moore, Brian T. Graham