Sih-Sian Wu

17 papers A* 1A 2C 6Journal 5Unranked 3
YearRankTypeTitle / Venue / Authors
2021 C conf
A Computational Efficient Architecture for Extremely Sparse Stereo Network.
ISCAS
Tan Huang, Sih-Sian Wu, Jan Klopp, Po-Hsiang Yu, Liang-Gee Chen
2021 J jnl
CMWMF: Constant Memory Architecture of Weighted Mode/Median Filter for Extremely Large Label Depth Refinement.
IEEE Trans. Circuits Syst. Video Technol.
Sih-Sian Wu, Liang-Gee Chen
2021 J jnl
Hardware- and Memory-Efficient Architecture for Disparity Estimation of Large Label Counts.
IEEE Trans. Circuits Syst. Video Technol.
Sih-Sian Wu, Hon-Hui Chen, Liang-Gee Chen
2021 J jnl
KCP: Kernel Cluster Pruning for Dense Labeling Neural Networks.
CoRR
Po-Hsiang Yu, Sih-Sian Wu, Liang-Gee Chen
2021 C conf
Online Training Refinement Network and Architecture Design for Stereo Matching.
ISCAS
Yu-Sheng Wu, Sih-Sian Wu, Tan Huang, Liang-Gee Chen
2020 J jnl
Joint Pruning & Quantization for Extremely Sparse Neural Networks.
CoRR
Po-Hsiang Yu, Sih-Sian Wu, Jan P. Klopp, Liang-Gee Chen, Shao-Yi Chien
2018 C conf
Accurate and Bandwidth Efficient Architecture for CNN-based Full-HD Super-Resolution.
ISCAS
Chung-Yan Chih, Sih-Sian Wu, Jan P. Klopp, Liang-Gee Chen
2018 A conf
Video Stereo Matching with Temporally Consistent Belief Propagation.
ICME
Hsin-Yu Hou, Sih-Sian Wu, Da-Fang Chang, Liang-Gee Chen
2017 C conf
Accurate and fast segment-based cost aggregation algorithm for stereo matching.
MMSP
Da-Fang Chang, Sih-Sian Wu, Hsin-Yu Hou, Liang-Gee Chen
2016 C conf
3-D perception enhancement in autostereoscopic TV by depth cue for 3-D model interaction.
ICCE
Yi-Ting Shen, Guan-Lin Liu, Sih-Sian Wu, Liang-Gee Chen
2016 — conf
Efficient Hardware Architecture for Large Disparity Range Stereo Matching Based on Belief Propagation.
SiPS
Sih-Sian Wu, Chen-Han Tsai, Liang-Gee Chen
2015 — conf
23.2 A 1920×1080 30fps 611 mW five-view depth-estimation processor for light-field applications.
ISSCC
Hong-Hui Chen, Chao-Tsung Huang, Sih-Sian Wu, Chia-Liang Hung, Tsung-Chuan Ma, Liang-Gee Chen
2015 C conf
Memory efficient architecture for belief propagation based disparity estimation.
ISCAS
Sih-Sian Wu, Hong-Hui Chen, Chen-Han Tsai, Liang-Gee Chen
2014 A conf
A thermal resilient integration of many-core microprocessors and main memory by 2.5D TSI I/Os.
DATE
Sih-Sian Wu, Kanwen Wang, Sai Manoj Pudukotai Dinakarrao, Tsung-Yi Ho, Mingbin Yu, Hao Yu
2011 J jnl
Model-Driven Design and Generation of New Multi-Facet Arbiters: From the Design Model to the Hardware Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jer-Min Jou, Yun-Lung Lee, Sih-Sian Wu
2010 — conf
Efficient design and generation of a multi-facet arbiter.
SASP
Jer-Min Jou, Yun-Lung Lee, Sih-Sian Wu
2010 A* conf
New model-driven design and generation of multi-facet arbiters part I: from the design model to the architecture model.
DAC
Jer-Min Jou, Sih-Sian Wu, Yun-Lung Lee, Cheng Chou, Yuan-Long Jeang