Sigang Ryu

17 papers C 1Journal 9Unranked 7
YearRankTypeTitle / Venue / Authors
2025 J jnl
A 28nm 1.80Mb/mm2 Digital/Analog Hybrid SRAM-CIM Macro Using 2D-Weighted Capacitor Array for Complex Number Mac Operations.
CoRR
Shota Konno, Che-Kai Liu, Sigang Ryu, Samuel Spetalnick, Arijit Raychowdhury
2025 J jnl
A 65-nm Delta-Sigma ADC-Based VDD-Variation-Tolerant Power-Side-Channel-Attack Sensor.
IEEE Solid State Circuits Lett.
Shota Konno, Zachary J. Ellis, Anupam Golder, Sigang Ryu, Daniel Dinu, Avinash Varna, Sanu Mathew, Arijit Raychowdhury
2025 J jnl
An Edge Accelerator With 5 MB of 0.256-pJ/bit Embedded RRAM and a Localization Solver for Bristle Robot Surveillance.
IEEE J. Solid State Circuits
Samuel D. Spetalnick, Ashwin Sanjay Lele, Brian Crafton, Muya Chang, Sigang Ryu, Jong-Hyeok Yoon, Zhijian Hao, Azadeh Ansari, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
2025 J jnl
MDS-DOA: Fusing Model-Based and Data-Driven Approaches for Modular, Distributed, and Scalable Direction-of-Arrival Estimation.
IEEE Trans. Circuits Syst. I Regul. Pap.
Adou Sangbone Assoa, Ashwin Bhat, Sigang Ryu, Arijit Raychowdhury
2024 — conf
30.1 A 40nm VLIW Edge Accelerator with 5MB of 0.256pJ/b RRAM and a Localization Solver for Bristle Robot Surveillance.
ISSCC
Samuel D. Spetalnick, Ashwin Sanjay Lele, Brian Crafton, Muya Chang, Sigang Ryu, Jong-Hyeok Yoon, Zhijian Hao, Azadeh Ansari, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury
2024 — conf
A 65nm Delta-Sigma ADC Based VDD-Variation-Tolerant Power-Side-Channel-Attack Monitor with Detection Capability Down to 0.25Ω.
VLSI Technology and Circuits
Shota Konno, Zachary J. Ellis, Anupam Golder, Sigang Ryu, Daniel Dinu, Avinash Varna, Sanu Mathew, Arijit Raychowdhury
2024 J jnl
Fractionally-Spaced Equalizers as Clock and Data Recovery Loops.
IEEE Trans. Circuits Syst. I Regul. Pap.
Sigang Ryu, Jaeha Kim, Arijit Raychowdhury
2023 — conf
A 65nm 60mW Dual-Loop Adaptive Digital Beamformer with Optimized Sidelobe Cancellation and On-Chip DOA Estimation for mm-Wave Applications.
VLSI Technology and Circuits
Sigang Ryu, Adou Sangbone Assoa, Shota Konno, Arijit Raychowdhury
2023 — conf
A Scalable Platform for Single-Snapshot Direction Of Arrival (DOA) Estimation in Massive MIMO Systems.
ACM Great Lakes Symposium on VLSI
Adou Sangbone Assoa, Ashwin Bhat, Sigang Ryu, Arijit Raychowdhury
2021 J jnl
A Time-Based Pipelined ADC Using Integrate-and-Fire Multiplying-DAC.
IEEE Trans. Circuits Syst. I Regul. Pap.
Sigang Ryu, Chan Young Park, Wooryeol Kim, Seuk Son, Jaeha Kim
2019 J jnl
A 2 × Blind Oversampling FSE Receiver With Combined Adaptive Equalization and Infinite-Range Timing Recovery.
IEEE J. Solid State Circuits
Seuk Son, Sigang Ryu, Hwanseok Yeo, Jaeha Kim
2019 J jnl
An Accurate and Noise-Resilient Spread-Spectrum Clock Tracking Aid for Digitally-Controlled Clock and Data Recovery Loops.
IEEE Trans. Circuits Syst. I Regul. Pap.
Sigang Ryu, Seuk Son, Jaeha Kim
2018 — conf
A 2× Blind Oversampling FSE Receiver with Combined Adaptive Equalization and Infinite-Range Timing Recovery.
A-SSCC
Seuk Son, Hwanseok Yeo, Sigang Ryu, Jaeha Kim
2016 — conf
13.1 A 940MHz-bandwidth 28.8µs-period 8.9GHz chirp frequency synthesizer PLL in 65nm CMOS for X-band FMCW radar applications.
ISSCC
Hwanseok Yeo, Sigang Ryu, Yoontaek Lee, Seuk Son, Jaeha Kim
2014 J jnl
A 9.2 GHz Digital Phase-Locked Loop With Peaking-Free Transfer Function.
IEEE J. Solid State Circuits
Sigang Ryu, Hwanseok Yeo, Yoontaek Lee, Seuk Son, Jaeha Kim
2013 — conf
A 9.2-GHz digital phase-locked loop with peaking-free transfer function.
CICC
Sigang Ryu, Hwanseok Yeo, Yoontaek Lee, Seuk Son, Jaeha Kim
2012 C conf
A model-first design and verification flow for analog-digital convergence systems: A high-speed receiver example in digital TVs.
ISCAS
Jaeha Kim, Sigang Ryu, Byoung-Joo Yoo, Hanseok Kim, Yunju Choi, Deog-Kyoon Jeong