Siddika Berna Örs

28 papers A 3B 2C 4Journal 6Unranked 13
YearRankTypeTitle / Venue / Authors
2021 J jnl
Comparison of RISC-V and transport triggered architectures for a postquantum cryptography application.
Turkish J. Electr. Eng. Comput. Sci.
Latif Akçay, Siddika Berna Örs
2020 — conf
Instruction Extension of an Open Source RV32IMC Core for NTRU Cryptosystem.
ECCTD
Elif Nur Isman, Canberk Topal, Latif Akçay, Siddika Berna Örs
2020 C ed.
SIN 2020: 13th International Conference on Security of Information and Networks, Virtual Event / Istanbul, Turkey, November 4-6, 2020
SIN
Siddika Berna Örs, Atilla Elçi
2015 — conf
Data transmission via GSM voice channel for end to end security.
ICCE-Berlin
Mehmet Akif Ozkan, Siddika Berna Örs
2015 — conf
Design of core blocks and implementation on a programmable logic controller for a train signalization system.
SIU
Burcu Akmansayar, Salman Kurtulan, Siddika Berna Örs
2014 J jnl
Analyzing and comparing the AES architectures for their power consumption.
J. Intell. Manuf.
Ahmet Dogan, Siddika Berna Örs, Gökay Saldamli
2014 — conf
Image filtering processor and its applications.
SIU
Ahmet Cagri Bagbaba, Siddika Berna Örs, Ahmet Turan Erozan
2013 — conf
Hardware/Software codesign for watermarking in DCT domain.
SIU
Ahmet Turan Erozan, Subutay Giray Baskir, Siddika Berna Örs
2013 — conf
Implementation of a secure RFID protocol.
SIU
Subutay Giray Baskir, Siddika Berna Örs
2011 C conf
Architectures for Fast Modular Multiplication.
DSD
Ahmet Aris, Siddika Berna Örs, Gökay Saldamli
2011 — conf
Implementation of a PUF Circuit on a FPGA.
NTMS
Mehmet Soybali, Siddika Berna Örs, Gökay Saldamli
2009 C ed.
Proceedings of the 2nd International Conference on Security of Information and Networks, SIN 2009, Gazimagusa, North Cyprus, October 6-10, 2009
SIN
Atilla Elçi, Oleg B. Makarevich, Mehmet A. Orgun, Alexander G. Chefranov, Josef Pieprzyk, Yuri Anatolievich Bryukhomitsky, Siddika Berna Örs
2008 C conf
Differential Power Analysis resistant hardware implementation of the RSA cryptosystem.
ISCAS
Keklik Alptekin Bayam, Siddika Berna Örs
2008 J jnl
Hardware implementation of an elliptic curve processor over GF(p) with Montgomery modular multiplier.
Int. J. Embed. Syst.
Siddika Berna Örs, Lejla Batina, Bart Preneel, Joos Vandewalle
2008 — conf
Low-cost implementations of NTRU for pervasive security.
ASAP
Ali Can Atici, Lejla Batina, Junfeng Fan, Ingrid Verbauwhede, Siddika Berna Örs
2007 J jnl
Differential power and electromagnetic attacks on a FPGA implementation of elliptic curve cryptosystems.
Comput. Electr. Eng.
Elke De Mulder, Siddika Berna Örs, Bart Preneel, Ingrid Verbauwhede
2007 — conf
Power Analysis Resistant Hardware Implementations of AES.
ICECS
Levent Ordu, Siddika Berna Örs
2004 J jnl
An FPGA Implementation of a Montgomery Multiplier Over GF(2^m).
Comput. Artif. Intell.
Nele Mentens, Siddika Berna Örs, Bart Preneel, Joos Vandewalle
2004 — conf
An FPGA implementation of an elliptic curve processor GF(2
ACM Great Lakes Symposium on VLSI
Nele Mentens, Siddika Berna Örs, Bart Preneel
2004 B conf
Flexible Hardware Design for RSA and Elliptic Curve Cryptosystems.
CT-RSA
Lejla Batina, Geeke Bruin-Muurling, Siddika Berna Örs
2004 B conf
Power Analysis Attacks Against FPGA Implementations of the DES.
FPL
François-Xavier Standaert, Siddika Berna Örs, Jean-Jacques Quisquater, Bart Preneel
2004 A conf
Power Analysis of an FPGA: Implementation of Rijndael: Is Pipelining a DPA Countermeasure?
CHES
François-Xavier Standaert, Siddika Berna Örs, Bart Preneel
2004 — conf
Power-Analysis Attack on an ASIC AES implementation.
ITCC (2)
Siddika Berna Örs, Frank K. Gürkaynak, Elisabeth Oswald, Bart Preneel
2003 A conf
Hardware Implementation of a Montgomery Modular Multiplier in a Systolic Array.
IPDPS
Siddika Berna Örs, Lejla Batina, Bart Preneel, Joos Vandewalle
2003 — conf
Hardware Implementation of an Elliptic Curve Processor over GF(p).
ASAP
Siddika Berna Örs, Lejla Batina, Bart Preneel, Joos Vandewalle
2003 J jnl
Hardware architectures for public key cryptography.
Integr.
Lejla Batina, Siddika Berna Örs, Bart Preneel, Joos Vandewalle
2003 A conf
Power-Analysis Attacks on an FPGA - First Experimental Results.
CHES
Siddika Berna Örs, Elisabeth Oswald, Bart Preneel
1999 — conf
Modeling Bit Multiplication Blocks for DSP Applications Using VHDL.
EUROMICRO
Siddika Berna Örs, Ahmet Dervisoglu