Siddhartha Nath

35 papers A* 5A 9C 3Journal 6Unranked 11

Year	Rank	Type	Title / Venue / Authors
2023	—	`conf`	BufFormer: A Generative ML Framework for Scalable Buffering. ASP-DAC Rongjian Liang, Siddhartha Nath, Anand Rajaram, Jiang Hu, Haoxing Ren
2023	J	`jnl`	ECO-GNN: Signoff Power Prediction Using Graph Neural Networks with Subgraph Approximation. ACM Trans. Design Autom. Electr. Syst. Yi-Chen Lu, Siddhartha Nath, Sai Pentapati, Sung Kyu Lim
2022	A*	`conf`	Generative self-supervised learning for gate sizing: invited. DAC Siddhartha Nath, Geraldo Pradipta, Corey Hu, Tian Yang, Brucek Khailany, Haoxing Ren
2022	A	`conf`	TransSizer: A Novel Transformer-Based Fast Gate Sizer. ICCAD Siddhartha Nath, Geraldo Pradipta, Corey Hu, Tian Yang, Brucek Khailany, Haoxing Ren
2022	A	`conf`	Why are Graph Neural Networks Effective for EDA Problems?: (Invited Paper). ICCAD Haoxing Ren, Siddhartha Nath, Yanqing Zhang, Hao Chen, Mingjie Liu
2021	A	`conf`	Doomed Run Prediction in Physical Design by Exploiting Sequential Flow and Graph Learning. ICCAD Yi-Chen Lu, Siddhartha Nath, Vishal Khandelwal, Sung Kyu Lim
2021	—	`conf`	Machine Learning-Enabled High-Frequency Low-Power Digital Design Implementation At Advanced Process Nodes. ISPD Siddhartha Nath, Vishal Khandelwal
2021	A	`conf`	Optimizing VLSI Implementation with Reinforcement Learning - ICCAD Special Session Paper. ICCAD Haoxing Ren, Saad Godil, Brucek Khailany, Robert Kirby, Haiguang Liao, Siddhartha Nath, Jonathan Raiman, Rajarshi Roy
2021	A*	`conf`	RL-Sizer: VLSI Gate Sizing for Timing Optimization using Deep Reinforcement Learning. DAC Yi-Chen Lu, Siddhartha Nath, Vishal Khandelwal, Sung Kyu Lim
2020	A	`conf`	A Fast Learning-Driven Signoff Power Optimization Framework. ICCAD Yi-Chen Lu, Siddhartha Nath, Sai Surya Kiran Pentapati, Sung Kyu Lim
2017	J	`jnl`	Optimal Scheduling and Allocation for IC Design Management and Cost Reduction. ACM Trans. Design Autom. Electr. Syst. Prabhav Agrawal, Mike Broxterman, Biswadeep Chatterjee, Patrick Cuevas, Kathy H. Hayashi, Andrew B. Kahng, Pranay K. Myana, Siddhartha Nath
2016	C	`conf`	BEOL stack-aware routability prediction from placement using data mining techniques. ICCD Wei-Ting Jonas Chan, Yang Du, Andrew B. Kahng, Siddhartha Nath, Kambiz Samadi
2016	—	`conf`	Learning-based prediction of embedded memory timing failures during initial floorplan design. ASP-DAC Wei-Ting Jonas Chan, Kun Young Chung, Andrew B. Kahng, Nancy D. MacDonald, Siddhartha Nath
2016	—	`—`	New Applications of Learning-Based Modeling in Nanoscale Integrated-Circuit Design. Siddhartha Nath
2015	A*	`conf`	3DIC benefit estimation and implementation guidance from 2DIC implementation. DAC Wei-Ting Jonas Chan, Siddhartha Nath, Andrew B. Kahng, Yang Du, Kambiz Samadi
2015	A*	`conf`	A global-local optimization framework for simultaneous multi-mode multi-corner clock skew variation reduction. DAC Kwangsoo Han, Jiajia Li, Andrew B. Kahng, Siddhartha Nath, Jongpil Lee
2015	J	`jnl`	ORION3.0: A Comprehensive NoC Router Estimation Tool. IEEE Embed. Syst. Lett. Andrew B. Kahng, Bill Lin, Siddhartha Nath
2015	J	`jnl`	Optimization of Overdrive Signoff in High-Performance and Low-Power ICs. IEEE Trans. Very Large Scale Integr. Syst. Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li, Siddhartha Nath, Bongil Park
2015	—	`conf`	SI for free: machine learning of interconnect coupling delay and transition effects. SLIP Andrew B. Kahng, Mulong Luo, Siddhartha Nath
2015	A	`conf`	Toward Metrics of Design Automation Research Impact. ICCAD Andrew B. Kahng, Mulong Luo, Gi-Joon Nam, Siddhartha Nath, David Z. Pan, Gabriel Robins
2014	A	`conf`	A deep learning methodology to proliferate golden signoff timing. DATE Seung-Soo Han, Andrew B. Kahng, Siddhartha Nath, Ashok S. Vydyanathan
2014	C	`conf`	ITRS 2.0: Toward a re-framing of the Semiconductor Technology Roadmap. ICCD Juan Antonio Carballo, Wei-Ting Jonas Chan, Paolo A. Gargini, Andrew B. Kahng, Siddhartha Nath
2014	—	`conf`	Methodology for electromigration signoff in the presence of adaptive voltage scaling. SLIP Wei-Ting Jonas Chan, Andrew B. Kahng, Siddhartha Nath
2014	—	`conf`	OCV-aware top-level clock tree optimization. ACM Great Lakes Symposium on VLSI Tuck-Boon Chan, Kwangsoo Han, Andrew B. Kahng, Jae-Gon Lee, Siddhartha Nath
2014	—	`conf`	Optimal reliability-constrained overdrive frequency selection in multicore systems. ISQED Andrew B. Kahng, Siddhartha Nath
2014	C	`conf`	The ITRS MPU and SOC system drivers: Calibration and implications for design-based equivalent scaling in the roadmap. ICCD Wei-Ting Jonas Chan, Andrew B. Kahng, Siddhartha Nath, Ichiro Yamamoto
2013	A	`conf`	Enhanced metamodeling techniques for high-dimensional IC design estimation problems. DATE Andrew B. Kahng, Bill Lin, Siddhartha Nath
2013	—	`conf`	High-dimensional metamodeling for prediction of clock tree synthesis outcomes. SLIP Andrew B. Kahng, Bill Lin, Siddhartha Nath
2013	A	`conf`	Incremental multiple-scan chain ordering for ECO flip-flop insertion. ICCAD Andrew B. Kahng, Ilgweon Kang, Siddhartha Nath
2013	—	`conf`	Learning-based approximation of interconnect delay and slew in signoff timing tools. SLIP Andrew B. Kahng, Seokhyeong Kang, Hyein Lee, Siddhartha Nath, Jyoti Wadhwani
2013	—	`conf`	On potential design impacts of electromigration awareness. ASP-DAC Andrew B. Kahng, Siddhartha Nath, Tajana Rosing
2013	—	`conf`	Optimization of overdrive signoff. ASP-DAC Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li, Siddhartha Nath
2012	A*	`conf`	Explicit modeling of control and data for improved NoC router estimation. DAC Andrew B. Kahng, Bill Lin, Siddhartha Nath
2012	J	`jnl`	Redefining the Role of the CPU in the Era of CPU-GPU Integration. IEEE Micro Manish Arora, Siddhartha Nath, Subhra Mazumdar, Scott B. Baden, Dean M. Tullsen
2011	J	`jnl`	The GreenDroid Mobile Application Processor: An Architecture for Silicon's Dark Future. IEEE Micro Nathan Goulding-Hotta, Jack Sampson, Ganesh Venkatesh, Saturnino Garcia, Joe Auricchio, Po-Chao Huang, Manish Arora, Siddhartha Nath, Vikram Bhatt, Jonathan Babb, Steven Swanson, Michael B. Taylor