Siddharth R. K.

32 papers C 4Misc 4Journal 8Unranked 16
YearRankTypeTitle / Venue / Authors
2026 Misc conf
A Robust CMOS Schmitt Trigger Architecture with Improved Noise Immunity and Hysteresis Control.
VLSID
Siddharth R. K., Shasidhar Reddy, Cheni Deepankar, Karteek Dokala, Vasantha M. H., Nithin Kumar Y. B.
2026 J jnl
MFDFA-Enhanced GAN: A Hardware-Optimized Architecture for Efficient Synthetic Image Generation.
IEEE Access
Charudatta Korde, K. G. Shreeharsha, Siddharth R. K., M. H. Vasantha, Y. B. Nithin Kumar
2026 Misc conf
Partial Product Grouping-Based Approximate Multipliers for Deep Learning Inference.
VLSID
Boggu Priestly Samarpana, Siddharth R. K., Geeta Shet, Nithin Kumar Y. B., Vasantha M. H.
2025 C conf
A 0.9 V Configurable Dual Mode Comparator using a Supply Boosting Technique.
ISCAS
Sourabh Mestry, Siddharth R. K., Nithin Kumar Y. B., Vasantha M. H., Edoardo Bonizzoni
2025 J jnl
Evolutionary-Enhanced GAN With Wavelet-Based Discrimination: A Hardware-Accelerated Architecture for Efficient Synthetic Image Generation.
IEEE Access
Charudatta Korde, K. G. Shreeharsha, Siddharth R. K., M. H. Vasantha, Y. B. Nithin Kumar
2025 J jnl
Generating Synthetic Data Using 2D Multifractal Detrended Fluctuation Analysis Generative Adversarial Networks.
IEEE Access
Charudatta Korde, K. G. Shreeharsha, Siddharth R. K., M. H. Vasantha, Y. B. Nithin Kumar
2024 J jnl
An Error Bound Particle Swarm Optimization for Analog Circuit Sizing.
IEEE Access
K. G. Shreeharsha, Siddharth R. K., M. H. Vasantha, Kumar Y. B. Nithin
2024 J jnl
N-Parallel Paths-Based D-Latch for High-Speed Applications.
IEEE Access
Rakhi R., Siddharth R. K., K. G. Shreeharsha, M. H. Vasantha, Nithin Kumar Yernad Balachandra
2024 — conf
Power Reduction of a Level Triggered D Flip-Flop using Clock Gating and Power Gating Techniques.
iSES
Yamana Ashok Kumar, Nithin Kumar Y. B., Vasantha M. H., Siddharth R. K.
2023 C conf
A 11-ns, 3.85-fJ, Deep Sub-threshold, Energy Efficient Level Shifter in 65-nm CMOS.
ISCAS
R. D. Balaji, Siddharth R. K., Sanmitra Bharat Naik, Y. B. Nithin Kumar, M. H. Vasantha, Edoardo Bonizzoni
2023 Misc conf
A 2.5 GHz, 1-Kb SRAM with Auxiliary Circuit Assisted Sense Amplifier in 65-nm CMOS Process.
VLSID
Rupesh D. Kadhao, Siddharth R. K., Nithin Kumar Y. B., Vasantha M. H., Devesh Dwivedi
2023 — conf
Approximate Three-Operand Binary Adder for Error-Resilient Applications.
iSES
Darshan Halliyavar, Siddharth R. K., Vasantha M. H., Nithin Kumar Y. B., Sithara Raveendran
2023 J jnl
Partition Bound Random Number-Based Particle Swarm Optimization for Analog Circuit Sizing.
IEEE Access
K. G. Shreeharsha, Siddharth R. K., M. H. Vasantha, Y. B. Nithin Kumar
2021 Misc conf
A 1 V Double-Balanced Mixer for 2.4-2.5 GHz ISM Band Applications.
VLSID
Sanmitra Bharat Naik, Siddharth R. K., Anirban Chatterjee, Kumar Y. B. Nithin, M. H. Vasantha, Ramnath Kini
2021 — conf
A 1-V, 10-bit, 250 MS/s, Current-Steering Segmented DAC for Video Applications.
ISVLSI
Shiv Chandra Kumar, Siddharth R. K., Nithin Kumar Y. B., M. H. Vasantha
2021 C conf
A 1-V, 5-Bit, 180-µW, Differential Pulse Position Modulation ADC in 65-nm CMOS Process.
ISCAS
Peta Guruprakashkumar, Siddharth R. K., Nithin Kumar Y. B., Vasantha M. H., Edoardo Bonizzoni
2020 — conf
A 1 V, 39 μ W, 5-bit Multi-Level Comparator based Flash ADC.
iSES
Nitish Kumar, Siddharth R. K., Nithin Y. B. Kumar, M. H. Vasantha
2020 J jnl
A 1-V, 3-GHz Strong-Arm Latch Voltage Comparator for High Speed Applications.
IEEE Trans. Circuits Syst.
Siddharth R. K., Y. Jaya Satyanarayana, Nithin Y. B. Kumar, M. H. Vasantha, Edoardo Bonizzoni
2020 — conf
A 1.8 V Quadrature Phase LC Oscillator for 5G Applications.
iSES
Sanmitra Bharat Naik, Siddharth R. K., Anirban Chatterjee, Nithin Kumar Y. B., M. H. Vasantha, Ramnath Kini
2020 — conf
A 1.8 V, Mode-Configurable Hybrid Smart ADC.
iSES
Tejas J. Shahane, Siddharth R. K., Kumar Y. B. Nithin, Vasantha M. H.
2020 — conf
A Novel Single Event Upset Tolerant 12T Memory Cell for Aerospace Applications.
ISVLSI
Suraj Dohar, Siddharth R. K., Vasantha M. H., Nithin Kumar Y. B.
2020 — conf
A Wideband 12 Phase Ring Oscillator for 5G Applications.
MWSCAS
Sanmitra Bharat Naik, Siddharth R. K., Anirban Chatterjee, Nithin Kumar Y. B., Vasantha M. H., Ramnath Kini
2020 J jnl
Power Saving Scheme for Process Corner Calibrated Standard Cell Based Flash ADC in Wireless Surveillance Applications.
SN Comput. Sci.
Siddharth R. K., Nithin Y. B. Kumar, M. H. Vasantha
2019 — conf
An Asynchronous Analog to Digital Converter for Video Camera Applications.
ISVLSI
Sunil R., Siddharth R. K., Nithin Y. B. Kumar, M. H. Vasantha
2019 — conf
Process Corner Calibration for Standard Cell Based Flash ADC.
iSES
Pradeep R., Siddharth R. K., Nithin Kumar Yernad Balachandra, Vasantha Moodabettu Harishchandra
2019 — conf
Two-Step Flash ADC Using Standard Cell Based Flash ADCs.
iSES
Rahul E., Siddharth R. K., Vivek Sharma, M. H. Vasantha, Nithin Kumar Yernad Balachandra
2018 C conf
A Low-Power Auxiliary Circuit for Level-Crossing ADCs in IoT-Sensor Applications.
ISCAS
Siddharth R. K., Kumar Y. B. Nithin, M. H. Vasantha, Edoardo Bonizzoni
2018 — conf
An Asynchronous Analog to Digital Converter for Surveillance Camera Applications.
ISVLSI
Siddharth R. K., Sunil R., Nithin Y. B. Kumar, M. H. Vasantha, Edoardo Bonizzoni
2018 — conf
Design of Area-Power-Delay Efficient Square Root Carry Select Adder.
iSES
Chetan Kamble, Siddharth R. K., Shivnarayan Patidar, M. H. Vasantha, Nithin Y. B. Kumar
2017 — conf
Design of 5-Bit Flash ADC Using Multiple Input Standard Cell Gates for Large Input Swing.
ISVLSI
Sumit Khalapure, Siddharth R. K., Kumar Y. B. Nithin, M. H. Vasantha
2017 — conf
Design of Low Power 4-Bit 400MS/s Standard Cell Based Flash ADC.
ISVLSI
S. M. Mayur, Siddharth R. K., Kumar Y. B. Nithin, M. H. Vasantha
2016 — conf
Design of Low Power 5-Bit Hybrid Flash ADC.
ISVLSI
S. M. Mayur, Siddharth R. K., Kumar Y. B. Nithin, M. H. Vasantha