Siddharth Joshi

63 papers A* 1A 3B 1C 6Misc 1Journal 30Unranked 20

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	An In-Situ Spatial-Temporal Sequence Detector for Neuromorphic Vision Sensor Empowered by High Density Vertical NAND Storage. CoRR Zijian Zhao, Varun Darshana Parekh, Po-Kai Hsu, Yixin Qin, Yiming Song, A. N. M. Nafiul Islam, Ningyuan Cao, Siddharth Joshi, Thomas Kämpfe, Moonyoung Jung, Kwangyou Seo, Kwangsoo Kim, Wanki Kim, Daewon Ha, Sourav Dutta, Abhronil Sengupta, Xiao Gong, Shimeng Yu, Vijaykrishnan Narayanan, Kai Ni
2025	C	`conf`	Hadamard-Walsh Channelized Receivers: Theory, Implementation, and Applications. ISCAS Adyant Balaji, Zhaoyi Liu, Siddharth Joshi, Gert Cauwenberghs
2025	J	`jnl`	Huff-LLM: End-to-End Lossless Compression for Efficient LLM Inference. CoRR Patrick Yubeaton, Tareq Mahmoud, Shehab Naga, Pooria Taheri, Tianhua Xia, Arun George, Yasmein Khalil, Sai Qian Zhang, Siddharth Joshi, Chinmay Hegde, Siddharth Garg
2025	J	`jnl`	Slax: a composable JAX library for rapid and flexible prototyping of spiking neural networks. Neuromorph. Comput. Eng. Thomas M. Summe, Siddharth Joshi
2024	J	`jnl`	A Remedy to Compute-in-Memory with Dynamic Random Access Memory: 1FeFET-1C Technology for Neuro-Symbolic AI. CoRR Xunzhao Yin, Hamza Errahmouni Barkam, Franz Müller, Yu Jiang, Mohsen Imani, Sukhrob Abdulazhanov, Alptekin Vardar, Nellie Laleni, Zijian Zhao, Jiahui Duan, Zhiguo Shi, Siddharth Joshi, Michael T. Niemier, Xiaobo Sharon Hu, Cheng Zhuo, Thomas Kämpfe, Kai Ni
2024	A	`conf`	Edge Inference with Fully Differentiable Quantized Mixed Precision Neural Networks. WACV Clemens J. S. Schaefer, Siddharth Joshi, Shan Li, Raúl Blázquez
2024	—	`conf`	Estimating Post-Synaptic Effects for Online Training of Feed-Forward SNNs. ICONS Thomas M. Summe, Clemens JS Schaefer, Siddharth Joshi
2024	—	`conf`	Hadamard Domain Training with Integers for Class Incremental Quantized Learning. CoLLAs Martin Schiemer, Clemens JS Schaefer, Mark James Horeni, Yu Emma Wang, Juan Ye, Siddharth Joshi
2024	J	`jnl`	Slax: A Composable JAX Library for Rapid and Flexible Prototyping of Spiking Neural Networks. CoRR Thomas Summe, Siddharth Joshi
2023	J	`jnl`	Augmenting Hessians with Inter-Layer Dependencies for Mixed-Precision Post-Training Quantization. CoRR Clemens JS Schaefer, Navid Lambert-Shirzad, Xiaofan Zhang, Chiachen Chou, Tom Jablin, Jian Li, Elfie Guo, Caitlin Stanton, Siddharth Joshi, Yu Emma Wang
2023	J	`jnl`	Estimating Post-Synaptic Effects for Online Training of Feed-Forward SNNs. CoRR Thomas Summe, Clemens JS Schaefer, Siddharth Joshi
2023	J	`jnl`	Hadamard Domain Training with Integers for Class Incremental Quantized Learning. CoRR Martin Schiemer, Clemens JS Schaefer, Jayden Parker Vap, Mark James Horeni, Yu Emma Wang, Juan Ye, Siddharth Joshi
2023	J	`jnl`	Improvements in Interlayer Pipelining of CNN Accelerators Using Genetic Algorithms. CoRR Mark Horeni, Siddharth Joshi
2023	J	`jnl`	Micro/Nano Circuits and Systems Design and Design Automation: Challenges and Opportunities. Proc. IEEE Gert Cauwenberghs, Jason Cong, X. Sharon Hu, Siddharth Joshi, Subhasish Mitra, Wolfgang Porod, H.-S. Philip Wong
2023	J	`jnl`	Mixed Precision Post Training Quantization of Neural Networks with Sensitivity Guided Search. CoRR Clemens JS Schaefer, Elfie Guo, Caitlin Stanton, Xiaofan Zhang, Tom Jablin, Navid Lambert-Shirzad, Jian Li, Chiachen Chou, Siddharth Joshi, Yu Emma Wang
2023	J	`jnl`	NeuroBench: Advancing Neuromorphic Computing through Collaborative, Fair and Representative Benchmarking. CoRR Jason Yik, Soikat Hasan Ahmed, Zergham Ahmed, Brian Anderson, Andreas G. Andreou, Chiara Bartolozzi, Arindam Basu, Douwe den Blanken, Petrut Bogdan, Sander M. Bohté, Younes Bouhadjar, Sonia M. Buckley, Gert Cauwenberghs, Federico Corradi, Guido de Croon, Andreea Danielescu, Anurag Reddy Daram, Mike Davies, Yigit Demirag, Jason Eshraghian, Jeremy Forest, Steve B. Furber, P. Michael Furlong, Aditya Gilra, Giacomo Indiveri, Siddharth Joshi, Vedant Karia, Lyes Khacef, James C. Knight, Laura Kriener, Rajkumar Kubendran, Dhireesha Kudithipudi, Gregor Lenz, Rajit Manohar, Christian Mayr, Konstantinos P. Michmizos, Dylan R. Muir, Emre Neftci, Thomas Nowotny, Fabrizio Ottati, Ayça Özcelikkale, Noah Pacik-Nelson, Priyadarshini Panda, Pao-Sheng Sun, Melika Payvand, Christian Pehle, Mihai A. Petrovici, Christoph Posch, Alpha Renner, Yulia Sandamirskaya, Clemens JS Schaefer, André van Schaik, Johannes Schemmel, Catherine D. Schuman, Jae-sun Seo, Sumit Bam Shrestha, Manolis Sifalakis, Amos Sironi, Kenneth Michael Stewart, Terrence C. Stewart, Philipp Stratmann, Guangzhi Tang, Jonathan Timcheck, Marian Verhelst, Craig M. Vineyard, Bernhard Vogginger, Amirreza Yousefzadeh, Biyan Zhou, Fatima Tuz Zohora, Charlotte Frenkel, Vijay Janapa Reddi
2023	J	`jnl`	The Hardware Impact of Quantization and Pruning for Weights in Spiking Neural Networks. CoRR Clemens JS Schaefer, Pooria Taheri, Mark Horeni, Siddharth Joshi
2023	J	`jnl`	The Hardware Impact of Quantization and Pruning for Weights in Spiking Neural Networks. IEEE Trans. Circuits Syst. II Express Briefs Clemens JS Schaefer, Pooria Taheri, Mark Horeni, Siddharth Joshi
2022	J	`jnl`	A compute-in-memory chip based on resistive random-access memory. Nat. Weier Wan, Rajkumar Kubendran, Clemens J. S. Schaefer, Sukru Burc Eryilmaz, Wenqiang Zhang, Dabin Wu, Stephen R. Deiss, Priyanka Raina, He Qian, Bin Gao, Siddharth Joshi, Huaqiang Wu, H.-S. Philip Wong, Gert Cauwenberghs
2022	J	`jnl`	Edge Inference with Fully Differentiable Quantized Mixed Precision Neural Networks. CoRR Clemens J. S. Schaefer, Siddharth Joshi, Shan Li, Raúl Blázquez
2022	B	`conf`	Ruby: Improving Hardware Efficiency for Tensor Algebra Accelerators Through Imperfect Factorization. ISPASS Mark Horeni, Pooria Taheri, Po-An Tsai, Angshuman Parashar, Joel S. Emer, Siddharth Joshi
2021	J	`jnl`	Edge AI without Compromise: Efficient, Versatile and Accurate Neurocomputing in Resistive Random-Access Memory. CoRR Weier Wan, Rajkumar Kubendran, Clemens J. S. Schaefer, Sukru Burc Eryilmaz, Wenqiang Zhang, Dabin Wu, Stephen R. Deiss, Priyanka Raina, He Qian, Bin Gao, Siddharth Joshi, Huaqiang Wu, H.-S. Philip Wong, Gert Cauwenberghs
2021	C	`conf`	LSTMs for Keyword Spotting with ReRAM-Based Compute-In-Memory Architectures. ISCAS Clemens J. S. Schaefer, Mark Horeni, Pooria Taheri, Siddharth Joshi
2020	—	`conf`	33.1 A 74 TMACS/W CMOS-RRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-situ Transposable Weights for Probabilistic Graphical Models. ISSCC Weier Wan, Rajkumar Kubendran, Sukru Burc Eryilmaz, Wenqiang Zhang, Yan Liao, Dabin Wu, Stephen R. Deiss, Bin Gao, Priyanka Raina, Siddharth Joshi, Huaqiang Wu, Gert Cauwenberghs, H.-S. Philip Wong
2020	—	`conf`	A 1.52 pJ/Spike Reconfigurable Multimodal Integrate-and-Fire Neuron Array Transceiver. ICONS Rajkumar Kubendran, Weier Wan, Siddharth Joshi, H.-S. Philip Wong, Gert Cauwenberghs
2020	C	`conf`	A 4.2-pJ/Conv 10-b Asynchronous ADC with Hybrid Two-Tier Level-Crossing Event Coding. ISCAS Rajkumar Kubendran, Jongkil Park, Ritvik Sharma, Chul Kim, Siddharth Joshi, Gert Cauwenberghs, Sohmyung Ha
2020	A*	`conf`	A Device Non-Ideality Resilient Approach for Mapping Neural Networks to Crossbar Arrays. DAC Arman Kazemi, Cristobal Alessandri, Alan C. Seabaugh, Xiaobo Sharon Hu, Michael T. Niemier, Siddharth Joshi
2020	J	`jnl`	A Device Non-Ideality Resilient Approach for Mapping Neural Networks to Crossbar Arrays. CoRR Arman Kazemi, Cristobal Alessandri, Alan C. Seabaugh, Xiaobo Sharon Hu, Michael T. Niemier, Siddharth Joshi
2020	—	`conf`	Analog vs. Digital Spatial Transforms: A Throughput, Power, and Area Comparison. MWSCAS Zephan M. Enciso, Seyed Hadi Mirfarshbafan, Oscar Castañeda, Clemens J. S. Schaefer, Christoph Studer, Siddharth Joshi
2020	J	`jnl`	Analog vs. Digital Spatial Transforms: A Throughput, Power, and Area Comparison. CoRR Zephan M. Enciso, Seyed Hadi Mirfarshbafan, Oscar Castañeda, Clemens J. S. Schaefer, Christoph Studer, Siddharth Joshi
2020	A	`conf`	Embedding error correction into crossbars for reliable matrix vector multiplication using emerging devices. ISLPED Qiuwen Lou, Tianqi Gao, Patrick Faley, Michael T. Niemier, Xiaobo Sharon Hu, Siddharth Joshi
2020	—	`conf`	Memory Organization and Structures for On-Chip Learning in Spiking Neural Networks. MWSCAS Clemens J. S. Schaefer, Siddharth Joshi
2020	C	`conf`	Memory Organization for Energy-Efficient Learning and Inference in Digital Neuromorphic Accelerators. ISCAS Clemens J. S. Schaefer, Patrick Faley, Emre O. Neftci, Siddharth Joshi
2020	J	`jnl`	Memory Organization for Energy-Efficient Learning and Inference in Digital Neuromorphic Accelerators. CoRR Clemens J. S. Schaefer, Patrick Faley, Emre O. Neftci, Siddharth Joshi
2020	—	`conf`	Quantizing Spiking Neural Networks with Integers. ICONS Clemens J. S. Schaefer, Siddharth Joshi
2019	J	`jnl`	Digitally Adaptive High-Fidelity Analog Array Signal Processing Resilient to Capacitive Multiplying DAC Inter-Stage Gain Error. IEEE Trans. Circuits Syst. I Regul. Pap. Siddharth Joshi, Chul Kim, Chris M. Thomas, Gert Cauwenberghs
2019	—	`conf`	DropOut and DropConnect for Reliable Neuromorphic Inference under Energy and Bandwidth Constraints in Network Connectivity. AICAS Yasufumi Sakai, Bruno U. Pedroni, Siddharth Joshi, Abraham Akinin, Gert Cauwenberghs
2019	J	`jnl`	Dropout and DropConnect for Reliable Neuromorphic Inference Under Communication Constraints in Network Connectivity. IEEE J. Emerg. Sel. Topics Circuits Syst. Yasufumi Sakai, Bruno U. Pedroni, Siddharth Joshi, Satoshi Tanabe, Abraham Akinin, Gert Cauwenberghs
2018	—	`conf`	A 92dB dynamic range sub-μVrms-noise 0.8μW/ch neural-recording ADC array with predictive digital autoranging. ISSCC Chul Kim, Siddharth Joshi, Hristos Courellis, Jun Wang, Cory T. Miller, Gert Cauwenberghs
2018	J	`jnl`	Sub-µV IEEE J. Solid State Circuits Chul Kim, Siddharth Joshi, Hristos Courellis, Jun Wang, Cory T. Miller, Gert Cauwenberghs
2018	—	`conf`	Unsupervised Synaptic Pruning Strategies for Restricted Boltzmann Machines. BioCAS Surabhi Kalyan, Siddharth Joshi, Sadique Sheik, Bruno U. Pedroni, Gert Cauwcnbcrghs
2017	—	`conf`	21.7 2pJ/MAC 14b 8×8 linear transform mixed-signal spatial filter in 65nm CMOS with 84dB interference suppression. ISSCC Siddharth Joshi, Chul Kim, Sohmyung Ha, Yu Mike Chi, Gert Cauwenberghs
2017	—	`conf`	From algorithms to devices: Enabling machine learning through ultra-low-power VLSI mixed-signal array processing. CICC Siddharth Joshi, Chul Kim, Sohmyung Ha, Gert Cauwenberghs
2017	J	`jnl`	Hierarchical Address Event Routing for Reconfigurable Large-Scale Neuromorphic Systems. IEEE Trans. Neural Networks Learn. Syst. Jongkil Park, Theodore Yu, Siddharth Joshi, Christoph Maier, Gert Cauwenberghs
2017	—	`—`	High-Fidelity Spatial Signal Processing in Low-Power Mixed-Signal VLSI Arrays Siddharth Joshi
2017	A	`conf`	Memristor for computing: Myth or reality? DATE Said Hamdioui, Shahar Kvatinsky, Gert Cauwenberghs, Lei Xie, Nimrod Wald, Siddharth Joshi, Hesham Mostafa Elsayed, Henk Corporaal, Koen Bertels
2017	Misc	`conf`	Neuromorphic event-driven multi-scale synaptic connectivity and plasticity. ACSSC Siddharth Joshi, Bruno U. Pedroni, Gert Cauwenberghs
2016	J	`jnl`	A 1.3 mW 48 MHz 4 Channel MIMO Baseband Receiver With 65 dB Harmonic Rejection and 48.5 dB Spatial Signal Separation. IEEE J. Solid State Circuits Chul Kim, Siddharth Joshi, Chris M. Thomas, Sohmyung Ha, Lawrence E. Larson, Gert Cauwenberghs
2016	J	`jnl`	A 6.5-µW/MHz Charge Buffer With 7-fF Input Capacitance in 65-nm CMOS for Noncontact Electropotential Sensing. IEEE Trans. Circuits Syst. II Express Briefs Siddharth Joshi, Chul Kim, Gert Cauwenberghs
2016	C	`conf`	A 6μW/MHz charge buffer with 7fF input capacitance in 65nm CMOS for non-contact electropotential sensing. ISCAS Siddharth Joshi, Chul Kim, Gert Cauwenberghs
2016	J	`jnl`	Energy Recycling Telemetry IC With Simultaneous 11.5 mW Power and 6.78 Mb/s Backward Data Delivery Over a Single 13.56 MHz Inductive Link. IEEE J. Solid State Circuits Sohmyung Ha, Chul Kim, Jongkil Park, Siddharth Joshi, Gert Cauwenberghs
2016	J	`jnl`	Forward Table-Based Presynaptic Event-Triggered Spike-Timing-Dependent Plasticity. CoRR Bruno U. Pedroni, Sadique Sheik, Siddharth Joshi, Georgios Detorakis, Somnath Paul, Charles Augustine, Emre Neftci, Gert Cauwenberghs
2016	—	`conf`	Forward table-based presynaptic event-triggered spike-timing-dependent plasticity. BioCAS Bruno U. Pedroni, Sadique Sheik, Siddharth Joshi, Georgios Detorakis, Somnath Paul, Charles Augustine, Emre Neftci, Gert Cauwenberghs
2016	—	`conf`	Neuromorphic architectures with electronic synapses. ISQED Sukru Burc Eryilmaz, Siddharth Joshi, Emre Neftci, Weier Wan, Gert Cauwenberghs, H.-S. Philip Wong
2016	J	`jnl`	Training a Probabilistic Graphical Model with Resistive Switching Electronic Synapses. CoRR Sukru Burc Eryilmaz, Emre Neftci, Siddharth Joshi, Sangbum Kim, Matthew BrightSky, Hsiang-Lan Lung, Chung Lam, Gert Cauwenberghs, H.-S. Philip Wong
2015	—	`conf`	A CMOS 4-channel MIMO baseband receiver with 65dB harmonic rejection over 48MHz and 50dB spatial signal separation over 3MHz at 1.3mW. VLSIC Chul Kim, Siddharth Joshi, Chris M. Thomas, Sohmyung Ha, Abraham Akinin, Lawrence E. Larson, Gert Cauwenberghs
2015	J	`jnl`	Unsupervised Learning in Synaptic Sampling Machines. CoRR Emre Neftci, Bruno U. Pedroni, Siddharth Joshi, Maruan Al-Shedivat, Gert Cauwenberghs
2014	—	`conf`	A 12.6 mW 8.3 Mevents/s contrast detection 128×128 imager with 75 dB intra-scene DR asynchronous random-access digital readout. BioCAS Jongkil Park, Sohmyung Ha, Chul Kim, Siddharth Joshi, Theodore Yu, Wei Ma, Gert Cauwenberghs
2014	—	`conf`	A 7.86 mW +12.5 dBm in-band IIP3 8-to-320 MHz capacitive harmonic rejection mixer in 65nm CMOS. ESSCIRC Chul Kim, Sohmyung Ha, Chris M. Thomas, Siddharth Joshi, Jongkil Park, Lawrence E. Larson, Gert Cauwenberghs
2014	—	`conf`	Energy-recycling integrated 6.78-Mbps data 6.3-mW power telemetry over a single 13.56-MHz inductive link. VLSIC Sohmyung Ha, Chul Kim, Jongkil Park, Siddharth Joshi, Gert Cauwenberghs
2012	—	`conf`	65k-neuron integrate-and-fire array transceiver with address-event reconfigurable synaptic routing. BioCAS Theodore Yu, Jongkil Park, Siddharth Joshi, Christoph Maier, Gert Cauwenberghs
2012	—	`conf`	Event-driven neural integration and synchronicity in analog VLSI. EMBC Theodore Yu, Jongkil Park, Siddharth Joshi, Christoph Maier, Gert Cauwenberghs
2012	C	`conf`	Live demonstration: Hierarchical Address-Event Routing architecture for reconfigurable large scale neuromorphic systems. ISCAS Jongkil Park, Theodore Yu, Christoph Maier, Siddharth Joshi, Gert Cauwenberghs