Siavash Bayat Sarmadi

49 papers A 1B 1C 1Journal 38Unranked 8
YearRankTypeTitle / Venue / Authors
2026 J jnl
Post-Quantum Authentication and Communication Security for Drone Networks.
IEEE Trans. Dependable Secur. Comput.
Parya Derakhshan Roodsari, Siavash Bayat Sarmadi, Hatameh Mosanaei-Boorani
2026 J jnl
iMAC: Toward Accelerating Deep Neural Networks by Predicting and Removing Ineffectual MAC Operations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Farhad Taheri, Siavash Bayat Sarmadi, Alireza Tabatabaeian
2024 J jnl
A Digital Signature Architecture Suitable for V2V Applications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hatameh Mosanaei-Boorani, Siavash Bayat Sarmadi
2024 J jnl
PartialHD: Toward Efficient Hyperdimensional Computing by Partial Processing.
IEEE Internet Things J.
Farhad Taheri, Siavash Bayat Sarmadi, Hamed Rastaghi
2023 J jnl
Comprehensive Evaluation of RSB and Spectre Vulnerability on Modern Processors.
CoRR
Farhad Taheri, Siavash Bayat Sarmadi, Alireza Sadeghpour, Seyed Parsa Tayefeh Morsal
2023 J jnl
Fixflow: A Framework to Evaluate Fixed-point Arithmetic in Light-Weight CNN Inference.
CoRR
Farhad Taheri, Siavash Bayat Sarmadi, Hatameh Mosanaei-Boorani, Reza Taheri
2023 J jnl
MISC: Multi-Input Secure Two-Party Computation.
ISC Int. J. Inf. Secur.
Farhad Taheri Ardakani, Siavash Bayat Sarmadi
2022 J jnl
A Study of Timing Side-Channel Attacks and Countermeasures on JavaScript and WebAssembly.
ISC Int. J. Inf. Secur.
Mohammad Erfan Mazaheri, Siavash Bayat Sarmadi, Farhad Taheri Ardakani
2022 J jnl
Efficient Hardware Implementations of Legendre Symbol Suitable for MPC Applications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Farhad Taheri, Siavash Bayat Sarmadi, Shahriar Ebrahimi
2022 J jnl
Fast Supersingular Isogeny Diffie-Hellman and Key Encapsulation Using a Customized Pipelined Montgomery Multiplier.
IEEE Trans. Circuits Syst. I Regul. Pap.
Mohammad Hossein Farzam, Siavash Bayat Sarmadi, Hatameh Mosanaei-Boorani, Armin Alivand
2022 J jnl
High-Speed Post-Quantum Cryptoprocessor Based on RISC-V Architecture for IoT.
IEEE Internet Things J.
Shahriar Hadayeghparast, Siavash Bayat Sarmadi, Shahriar Ebrahimi
2022 J jnl
RISC-HD: Lightweight RISC-V Processor for Efficient Hyperdimensional Computing Inference.
IEEE Internet Things J.
Farhad Taheri, Siavash Bayat Sarmadi, Shahriar Hadayeghparast
2021 J jnl
A Trusted Design Platform for Trojan Detection in FPGA Bitstreams Using Partial Reconfiguration.
ISC Int. J. Inf. Secur.
Nastaran Shekofte, Siavash Bayat Sarmadi, Hatameh Mosanaei-Boorani
2021 J jnl
Hardware Architecture for Supersingular Isogeny Diffie-Hellman and Key Encapsulation Using a Fast Montgomery Multiplier.
IEEE Trans. Circuits Syst. I Regul. Pap.
Mohammad Hossein Farzam, Siavash Bayat Sarmadi, Hatameh Mosanaei-Boorani, Armin Alivand
2021 J jnl
Lightweight Fuzzy Extractor Based on LPN for Device and Biometric Authentication in IoT.
IEEE Internet Things J.
Shahriar Ebrahimi, Siavash Bayat Sarmadi
2021 J jnl
PLCDefender: Improving Remote Attestation Techniques for PLCs Using Physical Model.
IEEE Internet Things J.
Mohsen Salehi, Siavash Bayat Sarmadi
2020 J jnl
Implementation of Supersingular Isogeny-Based Diffie-Hellman and Key Encapsulation Using an Efficient Scheduling.
IEEE Trans. Circuits Syst.
Mohammad Hossein Farzam, Siavash Bayat Sarmadi, Hatameh Mosanaei-Boorani
2020 J jnl
Lightweight and Fault-Resilient Implementations of Binary Ring-LWE for IoT Devices.
IEEE Internet Things J.
Shahriar Ebrahimi, Siavash Bayat Sarmadi
2020 — conf
Lurking Eyes: A Method to Detect Side-Channel Attacks on JavaScript and WebAssembly.
ISCISC
Mohammad Erfan Mazaheri, Farhad Taheri, Siavash Bayat Sarmadi
2019 J jnl
A Unified Approach to Detect and Distinguish Hardware Trojans and Faults in SRAM-based FPGAs.
J. Electron. Test.
Omid Ranjbar, Siavash Bayat Sarmadi, Fatemeh Pooyan, Hossein Asadi
2019 J jnl
An Efficient Low-Latency Point-Multiplication Over Curve25519.
IEEE Trans. Circuits Syst. I Regul. Pap.
Raziyeh Salarifard, Siavash Bayat Sarmadi
2019 — conf
High-Performance Fault Diagnosis Schemes for Efficient Hash Algorithm BLAKE.
LASCAS
Mehran Mozaffari Kermani, Siavash Bayat Sarmadi, A.-Bon E. Ackie, Reza Azarderakhsh
2019 J jnl
Low-Latency Double Point Multiplication Architecture Using Differential Addition Chain Over $GF(2^m)$.
IEEE Trans. Circuits Syst. I Regul. Pap.
Taha Shahroodi, Siavash Bayat Sarmadi, Hatameh Mosanaei-Boorani
2019 J jnl
Post-Quantum Cryptoprocessors Optimized for Edge and Resource-Constrained Devices in IoT.
IEEE Internet Things J.
Shahriar Ebrahimi, Siavash Bayat Sarmadi, Hatameh Mosanaei-Boorani
2019 J jnl
Toward On-chip Network Security Using Runtime Isolation Mapping.
ACM Trans. Archit. Code Optim.
Mohammad Sadegh Sadeghi, Siavash Bayat Sarmadi, Shaahin Hessabi
2018 J jnl
A Low-Latency and Low-Complexity Point-Multiplication in ECC.
IEEE Trans. Circuits Syst. I Regul. Pap.
Raziyeh Salarifard, Siavash Bayat Sarmadi, Hatameh Mosanaei-Boorani
2018 J jnl
Lightweight Hardware Architectures for Efficient Secure Hash Functions ECHO and Fugue.
CoRR
Mehran Mozaffari Kermani, Reza Azarderakhsh, Siavash Bayat Sarmadi
2018 — conf
Reliable hardware architectures for efficient secure hash functions ECHO and fugue.
CF
Mehran Mozaffari Kermani, Reza Azarderakhsh, Siavash Bayat Sarmadi
2017 — conf
Secure Two-Party Computation Using an Efficient Garbled Circuit by Reducing Data Transfer.
ATIS
Mohammad Hossein Yalame, Mohammad Hossein Farzam, Siavash Bayat Sarmadi
2016 J jnl
Efficient Lattice-based Authenticated Encryption: A Practice-Oriented Provable Security Approach.
IACR Cryptol. ePrint Arch.
Ahmad Boorghany, Siavash Bayat Sarmadi, Rasool Jalili
2016 J jnl
High-Throughput Low-Complexity Unified Multipliers Over GF(2
IEEE Trans. Circuits Syst. I Regul. Pap.
Raziyeh Salarifard, Siavash Bayat Sarmadi, Mohammad Farmani
2015 J jnl
FPGA-Based Protection Scheme against Hardware Trojan Horse Insertion Using Dummy Logic.
IEEE Embed. Syst. Lett.
Behnam Khaleghi, Ali Ahari, Hossein Asadi, Siavash Bayat Sarmadi
2015 J jnl
High-Throughput Low-Complexity Systolic Montgomery Multiplication Over GF(2
IEEE Trans. Circuits Syst. II Express Briefs
Siavash Bayat Sarmadi, Mohammad Farmani
2015 J jnl
On Constrained Implementation of Lattice-Based Cryptographic Primitives and Schemes on Smart Cards.
ACM Trans. Embed. Comput. Syst.
Ahmad Boorghany, Siavash Bayat Sarmadi, Rasool Jalili
2015 J jnl
Systolic Gaussian Normal Basis Multiplier Architectures Suitable for High-Performance Applications.
IEEE Trans. Very Large Scale Integr. Syst.
Reza Azarderakhsh, Mehran Mozaffari Kermani, Siavash Bayat Sarmadi, Chiou-Yng Lee
2014 J jnl
Dual-Basis Superserial Multipliers for Secure Applications and Lightweight Cryptographic Architectures.
IEEE Trans. Circuits Syst. II Express Briefs
Siavash Bayat Sarmadi, Mehran Mozaffari Kermani, Reza Azarderakhsh, Chiou-Yng Lee
2014 J jnl
Efficient and Concurrent Reliable Realization of the Secure Cryptographic SHA-3 Algorithm.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Siavash Bayat Sarmadi, Mehran Mozaffari Kermani, Arash Reyhani-Masoleh
2014 J jnl
Fault-Resilient Lightweight Cryptographic Block Ciphers for Secure Embedded Systems.
IEEE Embed. Syst. Lett.
Mehran Mozaffari Kermani, Kai Tian, Reza Azarderakhsh, Siavash Bayat Sarmadi
2014 J jnl
On Constrained Implementation of Lattice-based Cryptographic Primitives and Schemes on Smart Cards.
IACR Cryptol. ePrint Arch.
Ahmad Boorghany, Siavash Bayat Sarmadi, Rasool Jalili
2014 — conf
Random data and key generation evaluation of some commercial tokens and smart cards.
ISCISC
Ahmad Boorghany, Siavash Bayat Sarmadi, Pamian Yousefi, Pouneh Gorji, Rasool Jalili
2014 J jnl
Reliable Concurrent Error Detection Architectures for Extended Euclidean-Based Division Over GF(2
IEEE Trans. Very Large Scale Integr. Syst.
Mehran Mozaffari Kermani, Reza Azarderakhsh, Chiou-Yng Lee, Siavash Bayat Sarmadi
2009 J jnl
Concurrent Error Detection in Finite-Field Arithmetic Operations Using Pipelined and Systolic Architectures.
IEEE Trans. Computers
Siavash Bayat Sarmadi, M. Anwar Hasan
2007 C conf
Detecting errors in a polynomial basis multiplier using multiple parity bits for both inputs.
ICCD
Siavash Bayat Sarmadi, M. Anwar Hasan
2007 J jnl
On Concurrent Detection of Errors in Polynomial Basis Multiplication.
IEEE Trans. Very Large Scale Integr. Syst.
Siavash Bayat Sarmadi, M. Anwar Hasan
2007 — conf
Run-Time Error Detection in Polynomial Basis Multiplication Using Linear Codes.
ASAP
Siavash Bayat Sarmadi, M. Anwar Hasan
2005 — conf
Concurrent Error Detection of Polynomial Basis Multiplication over Extension Fields using a Multiple-bit Parity Scheme.
DFT
Siavash Bayat Sarmadi, M. Anwar Hasan
2003 A conf
A Hybrid Fault Injection Approach Based on Simulation and Emulation Co-operation.
DSN
Ali Reza Ejlali, Seyed Ghassem Miremadi, Hamid R. Zarandi, Ghazanfar Asadi, Siavash Bayat Sarmadi
2002 B conf
Fast Prototyping with Co-operation of Simulation and Emulation.
FPL
Siavash Bayat Sarmadi, Seyed Ghassem Miremadi, Ghazanfar Asadi, Ali Reza Ejlali
2002 — conf
Speedup analysis in simulation-emulation co-operation.
FPT
Seyed Ghassem Miremadi, Siavash Bayat Sarmadi, Ghazanfar Asadi