Siang-Yun Lee

18 papers A* 3A 4C 1Journal 8Unranked 2
YearRankTypeTitle / Venue / Authors
2025 J jnl
Benchmarking of Scaled Majority-Logic-Synthesized Spintronic Circuits Based on Magnetic Tunnel Junction Transducers.
IEEE Trans. Circuits Syst. I Regul. Pap.
Fanfan Meng, Siang-Yun Lee, Odysseas Zografos, Mohit Gupta, Van D. Nguyen, Giovanni De Micheli, Sorin Cotofana, Inge Asselberghs, Christoph Adelmann, Gouri Sankar Kar, Sebastien Couet, Florin Ciubotaru
2025 A* conf
Logic Restructuring with Preserved Logic Blocks.
DAC
Siang-Yun Lee, Heinz Riener, Sascha Richter, Ankush Sood
2025 J jnl
Technology Legalization and Optimization for Adiabatic Quantum-Flux Parametron.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Siang-Yun Lee, Alessandro Tempia Calvino, Heinz Riener, Giovanni De Micheli
2024 A* conf
Late Breaking Results: Majority-Inverter Graph Minimization by Design Space Exploration.
DAC
Siang-Yun Lee, Alessandro Tempia Calvino, Heinz Riener, Giovanni De Micheli
2024 A conf
Technology-Aware Logic Synthesis for Superconducting Electronics.
DATE
Rassul Bairamkulov, Siang-Yun Lee, Alessandro Tempia Calvino, Dewmini Sudara Marakkalage, Mingfei Yu, Giovanni De Micheli
2023 J jnl
AnySyn: A Cost-Generic Logic Synthesis Framework with Customizable Cost Functions.
CoRR
Hanyu Wang, Siang-Yun Lee, Giovanni De Micheli
2023 J jnl
Heuristic Logic Resynthesis Algorithms at the Core of Peephole Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Siang-Yun Lee, Giovanni De Micheli
2022 J jnl
A Simulation-Guided Paradigm for Logic Synthesis and Verification.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Siang-Yun Lee, Heinz Riener, Alan Mishchenko, Robert K. Brayton, Giovanni De Micheli
2022 J jnl
An Automated Testing and Debugging Toolkit for Gate-Level Logic Synthesis Applications.
CoRR
Siang-Yun Lee, Heinz Riener, Giovanni De Micheli
2022 A* conf
Beyond local optimality of buffer and splitter insertion for AQFP circuits.
DAC
Siang-Yun Lee, Heinz Riener, Giovanni De Micheli
2022 — conf
Boolean Rewriting Strikes Back: Reconvergence-Driven Windowing Meets Resynthesis.
ASP-DAC
Heinz Riener, Siang-Yun Lee, Alan Mishchenko, Giovanni De Micheli
2022 A conf
Majority-based Design Flow for AQFP Superconducting Family.
DATE
Giulia Meuli, Vinicius N. Possani, Rajinder Singh, Siang-Yun Lee, Alessandro Tempia Calvino, Dewmini Sudara Marakkalage, Patrick Vuillod, Luca G. Amarù, Scott Chase, Jamil Kawa, Giovanni De Micheli
2021 — conf
Algebraic and Boolean Optimization Methods for AQFP Superconducting Circuits.
ASP-DAC
Eleonora Testa, Siang-Yun Lee, Heinz Riener, Giovanni De Micheli
2021 J jnl
Irredundant Buffer and Splitter Insertion and Scheduling-Based Optimization for AQFP Circuits.
CoRR
Siang-Yun Lee, Heinz Riener, Giovanni De Micheli
2021 C conf
Logic Resynthesis of Majority-Based Circuits by Top-Down Decomposition.
DDECS
Siang-Yun Lee, Heinz Riener, Giovanni De Micheli
2020 J jnl
Simulation-Guided Boolean Resubstitution.
CoRR
Siang-Yun Lee, Heinz Riener, Alan Mishchenko, Robert K. Brayton, Giovanni De Micheli
2019 A conf
Searching Parallel Separating Hyperplanes for Effective Compression of Threshold Logic Networks.
ICCAD
Siang-Yun Lee, Nian-Ze Lee, Jie-Hong R. Jiang
2018 A conf
Canonicalization of threshold logic representation and its applications.
ICCAD
Siang-Yun Lee, Nian-Ze Lee, Jie-Hong R. Jiang