Shyue-Kung Lu - RankMe

95 papers A 3B 1C 11Journal 32Unranked 48

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Highly Efficient Built-In Self-Repair Techniques for NAND Flash Memory With Fine-Grained Redundancies. IEEE Access Shyue-Kung Lu, Shi-Chun Tseng, Kohei Miyase
2025	B	`conf`	Synergistic Built-In ECC Repair (BIER) Technique for Enhancing Yield and Reliability of Flash Memory. ETS Shyue-Kung Lu, Chun-Kai Chao, Kohei Miyase
2025	—	`conf`	Two-Step Transition Zeroization Techniques for MLC STTMRAM. ATS Shyue-Kung Lu, Tzu-En Huang, Kohei Miyase
2024	—	`conf`	Detectability of Resistive Open Defects with Analog Relaxation Oscillators Under Unit-to-Unit Variations of Dies. 3DIC Yuya Yamahashi, Yuto Ohtera, Hiroyuki Yotsuyanagi, Shyue-Kung Lu, Masaki Hashizume
2023	J	`jnl`	E J. Electron. Test. Shyue-Kung Lu, Zeng-Long Tsai
2023	—	`conf`	Integrated Progressive Built-In Self-Repair (IPBISR) Techniques for NAND Flash Memory. ITC-Asia Shyue-Kung Lu, Xin Dong
2022	—	`conf`	Effective Switching Probability Calculation to Locate Hotspots in Logic Circuits. ITC-Asia Taiki Utsunomiya, Ryu Hoshino, Kohei Miyase, Shyue-Kung Lu, Xiaoqing Wen, Seiji Kajihara
2022	—	`conf`	Enhanced Interconnect Test Method for Resistive Open Defects in Final Tests with Relaxation Oscillators. ATS Masao Ohmatsu, Yuto Ohtera, Yuki Ikiri, Hiroyuki Yotsuyanagi, Shyue-Kung Lu, Masaki Hashizume
2022	—	`conf`	Fault Resilience Techniques for Flash Memory of DNN Accelerators. ITC-Asia Shyue-Kung Lu, Yu-Sheng Wu, Jin-Hua Hong, Kohei Miyase
2022	A	`conf`	Fault Resilience Techniques for Flash Memory of DNN Accelerators. ITC Shyue-Kung Lu, Yu-Sheng Wu, Jin-Hua Hong, Kohei Miyase
2022	—	`conf`	Fault Securing Techniques for Yield and Reliability Enhancement of RRAM. ATS Shyue-Kung Lu, Zhi-Jia Liu, Masaki Hashizume
2022	A	`conf`	Fine-Grained Built-In Self-Repair Techniques for NAND Flash Memories. ITC Shyue-Kung Lu, Shi-Chun Tseng, Kohei Miyase
2021	J	`jnl`	Fault-Aware Dependability Enhancement Techniques for Phase Change Memory. J. Electron. Test. Shyue-Kung Lu, Hui-Ping Li, Kohei Miyase, Chun-Lung Hsu, Chi-Tien Sun
2020	—	`conf`	ECC Caching Techniques for Protecting NAND Flash Memories. ITC-Asia Shyue-Kung Lu, Zeng-Long Tsai, Chun-Lung Hsu, Chi-Tien Sun
2020	J	`jnl`	Fault-Aware Dependability Enhancement Techniques for Flash Memories. IEEE Trans. Very Large Scale Integr. Syst. Shyue-Kung Lu, Shu-Chi Yu, Chun-Lung Hsu, Chi-Tien Sun, Masaki Hashizume, Hiroyuki Yotsuyanagi
2020	—	`conf`	Fault-Aware ECC Techniques for Reliability Enhancement of Flash Memory. VLSI-DAT Shyue-Kung Lu, Zeng-Long Tsai, Chun-Lung Hsu, Chi-Tien Sun
2019	—	`conf`	A Fault-Tolerant MPSoC For CubeSats. DFT Christian M. Fuchs, Pai H. Chou, Xiaoqing Wen, Nadia M. Murillo, Gianluca Furano, Stefan Holst, Antonis Tavoularis, Shyue-Kung Lu, Aske Plaat, Kostas Marinis
2019	—	`conf`	A Static Method for Analyzing Hotspot Distribution on the LSI. ITC-Asia Kohei Miyase, Yudai Kawano, Shyue-Kung Lu, Xiaoqing Wen, Seiji Kajihara
2019	—	`conf`	Electrical Field Test Method of Resistive Open Defects between Dies by Quiescent Currents through Embedded Diodes. 3DIC Hanna Soneda, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu
2019	J	`jnl`	Retention-Aware Refresh Techniques for Reducing Power and Mitigation of Data Retention Faults in DRAM. J. Electron. Test. Shyue-Kung Lu, Hung-Kai Huang, Chun-Lung Hsu, Chi-Tien Sun, Kohei Miyase
2018	J	`jnl`	A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs. IEICE Trans. Inf. Syst. Fara Ashikin, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu, Zvi Roth
2018	C	`conf`	Adaptive ECC Techniques for Reliability and Yield Enhancement of Phase Change Memory. IOLTS Shyue-Kung Lu, Hui-Ping Li, Kohei Miyase
2018	J	`jnl`	Address Remapping Techniques for Enhancing Fabrication Yield of Embedded Memories. J. Electron. Test. Shyue-Kung Lu, Hao-Cheng Jheng, Hao-Wei Lin, Masaki Hashizume
2018	J	`jnl`	Fault Leveling Techniques for Yield and Reliability Enhancement of NAND Flash Memories. J. Electron. Test. Shyue-Kung Lu, Shang-Xiu Zhong, Masaki Hashizume
2018	—	`conf`	Progressive ECC Techniques for Phase Change Memory. ATS Shyue-Kung Lu, Hui-Ping Li, Kohei Miyase
2017	—	`conf`	A defect level monitor of resistive open defect at interconnects in 3D ICs by injected charge volume. ISCIT Kouhei Ohtani, Naho Osato, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu
2017	—	`conf`	A defective level monitor of open defects in 3D ICs with a comparator of offset cancellation type. DFT Michiya Kanda, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu
2017	—	`conf`	Adaptive block-based refresh techniques for mitigation of data retention faults and reduction of refresh power. ITC-Asia Shyue-Kung Lu, Hung-Kai Huang
2017	—	`conf`	Fault-Aware Page Address Remapping Techniques for Enhancing Yield and Reliability of Flash Memories. ATS Shyue-Kung Lu, Shu-Chi Yu, Masaki Hashizume, Hiroyuki Yotsuyanagi
2017	—	`conf`	Open Defect Detection with a Built-in Test Circuit by IDDT Appearance Time in CMOS ICs. ATS Ayumu Kambara, Hiroyuki Yotsuyanagi, Daichi Miyoshi, Masaki Hashizume, Shyue-Kung Lu
2016	J	`jnl`	A Built-in Test Circuit for Electrical Interconnect Testing of Open Defects in Assembled PCBs. IEICE Trans. Inf. Syst. Widianto, Masaki Hashizume, Shohei Suenaga, Hiroyuki Yotsuyanagi, Akira Ono, Shyue-Kung Lu, Zvi Roth
2016	—	`conf`	Adaptive ECC Techniques for Yield and Reliability Enhancement of Flash Memories. ATS Shyue-Kung Lu, Shang-Xiu Zhong, Masaki Hashizume
2016	J	`jnl`	Enhanced Built-In Self-Repair Techniques for Improving Fabrication Yield and Reliability of Embedded Memories. IEEE Trans. Very Large Scale Integr. Syst. Shyue-Kung Lu, Cheng-Ju Tsai, Masaki Hashizume
2016	—	`conf`	Integrated Heterogeneous Infrastructure for Indoor Positioning. SpaCCS Workshops Yi-Wei Ma, Jiann-Liang Chen, Yao-Hong Tsai, Pen-Chan Chou, Shyue-Kung Lu, Sy-Yen Kuo
2016	A	`conf`	Online slack-time binning for IO-registered die-to-die interconnects. ITC Chih-Chieh Zheng, Shi-Yu Huang, Shyue-Kung Lu, Ting-Chi Wang, Kun-Han Tsai, Wu-Tung Cheng
2015	J	`jnl`	Address Scrambling and Data Inversion Techniques for Yield Enhancement of NROM-Based ROMs. IEEE Trans. Computers Shyue-Kung Lu, Tsu-Lin Li, Masaki Hashizume, Jiann-Liang Chen
2015	—	`conf`	An enhanced built-in self-repair technique for yield and reliability improvement of embedded memories. ASICON Shyue-Kung Lu, Hao-Wei Lin, Masaki Hashizume
2015	—	`conf`	Electrical interconnect test method of 3D ICs by injected charge volume. 3DIC Daisuke Suga, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu
2015	—	`conf`	Electrical interconnect test of 3D ICs made of dies without ESD protection circuits with a built-in test circuit. 3DIC Kosuke Nanbara, Akihiro Odoriba, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu
2015	—	`conf`	Hybrid scrambling technique for increasing the fabrication yield of NROM-Based ROMs. VLSI-DAT Shyue-Kung Lu, Shu-Ling Lin, Hao-Wei Lin, Masaki Hashizume
2015	—	`conf`	Integration of Hard Repair Techniques with ECC for Enhancing Fabrication Yield and Reliability of Embedded Memories. ATS Shyue-Kung Lu, Cheng-Ju Tsai, Masaki Hashizume
2014	J	`jnl`	A Power Saving Mechanism for Multimedia Streaming Services in Cloud Computing. IEEE Syst. J. Yi-Wei Ma, Jiann-Liang Chen, Ching-Hesign Chou, Shyue-Kung Lu
2014	—	`conf`	A built-in supply current test circuit for electrical interconnect tests of 3D ICs. 3DIC Masaki Hashizume, Shoichi Umezu, Hiroyuki Yotsuyanagi, Shyue-Kung Lu
2014	—	`conf`	Built-In Scrambling Analysis for Yield Enhancement of Embedded Memories. ATS Shyue-Kung Lu, Hao-Cheng Jheng, Hao-Wei Lin, Masaki Hashizume, Seiji Kajihara
2014	—	`conf`	Efficient test length reduction techniques for interposer-based 2.5D ICs. VLSI-DAT Shyue-Kung Lu, Huai-Min Li, Masaki Hashizume, Jin-Hua Hong, Zheng-Ru Tsai
2013	J	`jnl`	An Efficient Test and Repair Flow for Yield Enhancement of One-Time-Programming NROM-Based ROMs. IEICE Trans. Inf. Syst. Tsu-Lin Li, Masaki Hashizume, Shyue-Kung Lu
2013	—	`conf`	Efficient test and repair architectures for 3D TSV-based random access memories. VLSI-DAT Shyue-Kung Lu, Uang-Chang Lu, Seng-Wen Pong, Hao-Cheng Cheng
2013	C	`conf`	Error-tolerance evaluation and design techniques for motion estimation computing arrays. IOLTS Shyue-Kung Lu, Ming-Chang Chen, Yen-Chi Chen
2013	—	`conf`	Fault Scrambling Techniques for Yield Enhancement of Embedded Memories. Asian Test Symposium Shyue-Kung Lu, Hao-Cheng Jheng, Masaki Hashizume, Jiun-Lang Huang, Pony Ning
2013	J	`jnl`	Synergistic Reliability and Yield Enhancement Techniques for Embedded SRAMs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shyue-Kung Lu, Huan-Hua Huang, Jiun-Lang Huang, Pony Ning
2013	—	`conf`	Testable Design for Electrical Testing of Open Defects at Interconnects in 3D ICs. Asian Test Symposium Masaki Hashizume, Tomoaki Konishi, Hiroyuki Yotsuyanagi, Shyue-Kung Lu
2012	J	`jnl`	Efficient Built-In Self-Repair Techniques for Multiple Repairable Embedded RAMs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shyue-Kung Lu, Zhen-Yu Wang, Yi-Ming Tsai, Jiann-Liang Chen
2012	J	`jnl`	Improving Reusability of Test Symbols for Test Data Compression. J. Inf. Sci. Eng. Shyue-Kung Lu, Ya-Chen Huang
2012	—	`conf`	On test and repair of 3D random access memory. ASP-DAC Cheng-Wen Wu, Shyue-Kung Lu, Jin-Fu Li
2012	—	`conf`	Scrambling and Data Inversion Techniques for Yield Enhancement of NROM-Based ROMs. Asian Test Symposium Shyue-Kung Lu, Tsu-Lin Li, Pony Ning
2012	J	`jnl`	Yield enhancement techniques for 3-dimensional random access memories. Microelectron. Reliab. Shyue-Kung Lu, Tin-Wei Chang, Han-Yu Hsu
2011	J	`jnl`	Speeding Up Emulation-Based Diagnosis Techniques for Logic Cores. IEEE Des. Test Comput. Shyue-Kung Lu, Yin Chen, Shi-Yu Huang, Cheng Wu
2010	J	`jnl`	Efficient BISR Techniques for Embedded Memories Considering Cluster Faults. IEEE Trans. Very Large Scale Integr. Syst. Shyue-Kung Lu, Chun-Lin Yang, Yuang-Cheng Hsiao, Cheng-Wen Wu
2009	C	`conf`	Built-In Self-Repair Techniques for Heterogeneous Memory Cores. PRDC Zhen-Yu Wang, Yi-Ming Tsai, Shyue-Kung Lu
2007	C	`conf`	Efficient BISR Techniques for Embedded Memories Considering Cluster Faults. PRDC Chun-Lin Yang, Yuang-Cheng Hsiao, Shyue-Kung Lu
2007	J	`jnl`	Low-Power Built-In Self-Test Techniques for Embedded SRAMs. VLSI Design Shyue-Kung Lu, Yuang-Cheng Hsiao, Chia-Hsiu Liu, Chun-Lin Yang
2006	—	`conf`	A Scalable Port Forwarding for P2P-Based Wi-Fi Applications. WASA Ming-Wei Wu, Yennun Huang, Ing-Yi Chen, Shyue-Kung Lu, Sy-Yen Kuo
2006	—	`conf`	Efficient BISR Techniques for Word-Oriented Embedded Memories with Hierarchical Redundancy. ACIS-ICIS Shyue-Kung Lu, Chun-Lin Yang, Han-Wen Lin
2006	C	`conf`	Efficient Built-In Self-Test Schemes for Video Coding Cores: a Case Study on DCT/IDCT Circuits. PRDC Shyue-Kung Lu, Ting-Yu Chen, Wei-Yuan Liu
2006	J	`jnl`	Efficient built-in redundancy analysis for embedded memories with 2-D redundancy. IEEE Trans. Very Large Scale Integr. Syst. Shyue-Kung Lu, Yu-Chen Tsai, Chih-Hsien Hsu, Kuo-Hua Wang, Cheng-Wen Wu
2006	J	`jnl`	Fault tolerance techniques for high capacity RAM. IEEE Trans. Reliab. Shyue-Kung Lu, Chih-Hsien Hsu
2005	—	`conf`	A BIRA algorithm for embedded memories with 2D redundancy. MTDT Shyue-Kung Lu, Yu-Cheng Tsai, Shih-Chang Huang
2005	C	`conf`	A Multi-Faceted Approach towards Spam-Resistible Mail. PRDC Ming-Wei Wu, Yennun Huang, Shyue-Kung Lu, Ing-Yi Chen, Sy-Yen Kuo
2005	J	`jnl`	Design-for-testability and fault-tolerant techniques for FFT processors. IEEE Trans. Very Large Scale Integr. Syst. Shyue-Kung Lu, Jen-Sheng Shih, Shih-Chang Huang
2004	—	`conf`	Built-in Self-Test and Repair (BISTR) Techniques for Embedded RAMs. MTDT Shyue-Kung Lu, Shih-Chang Huang
2004	J	`jnl`	Defect Level Prediction Using Multi-Model Fault Coverage. IEICE Trans. Inf. Syst. Shyue-Kung Lu
2004	C	`conf`	Efficient Built-in Self-Test Techniques for Memory-Based FFT Processors. PRDC Shyue-Kung Lu, Chien-Hung Yeh, Han-Wen Lin
2004	—	`conf`	Enhancing Delay Fault Testability for FIR Filters Based on Realistic Sequential Cell Fault Model. DELTA Shyue-Kung Lu, Mau-Jung Lu
2004	—	`conf`	Testing and Diagnosis Techniques for LUT-Based FPGA's. Asian Test Symposium Shyue-Kung Lu, Hung-Chin Wu, Shoei-Jia Yan, Yu-Cheng Tsai
2003	J	`jnl`	A Novel Built-In Self-Repair Approach for Embedded RAMs. J. Electron. Test. Shyue-Kung Lu
2003	—	`conf`	Combinational circuit fault diagnosis using logic emulation. ISCAS (5) Shyue-Kung Lu, Jian-Long Chen, Cheng-Wen Wu, Ken-Feng Chang, Shi-Yu Huang
2003	J	`jnl`	Efficient Double Fault Diagnosis for CMOS Logic Circuits With a Specific Application to Generic Bridging Faults. J. Inf. Sci. Eng. Hong-Chou Kao, Ming-Fu Tsai, Shi-Yu Huang, Cheng-Wen Wu, Wen-Feng Chang, Shyue-Kung Lu
2002	—	`conf`	Easily Testable and Fault-Tolerant Design of FFT Butterfly Networks. Asian Test Symposium Shyue-Kung Lu, Chien-Hung Yeh
2002	C	`conf`	Enhancing Delay Fault Testability for Iterative Logic Array. PRDC Shyue-Kung Lu, Chien-Hung Yeh
2002	J	`jnl`	Fault Detection and Fault Diagnosis Techniques for Lookup Table FPGAs. VLSI Design Shyue-Kung Lu, Fu-Min Yeh, Jen-Sheng Shih
2002	—	`conf`	Fault Detection and Fault Diagnosis Technoques for Lookup Table FPGA's. Asian Test Symposium Shyue-Kung Lu, Chung-Yang Chen
2002	—	`conf`	Fault-tolerance design of memory systems based on DBL structures. APCCAS (1) Chih-Hsien Hsu, Shyue-Kung Lu
2002	J	`jnl`	OBDD-based evaluation of k-terminal network reliability. IEEE Trans. Reliab. Fu-Min Yeh, Shyue-Kung Lu, Sy-Yen Kuo
2001	—	`conf`	A Profit Evaluation System (PES) for logic cores at early design stage. ICECS Shyue-Kung Lu, Tsung-Ying Lee, Cheng-Wen Wu
2001	—	`conf`	Built-In self-repair for divided word line memory. ISCAS (4) Shyue-Kung Lu, Chih-Hsien Hsu
2001	C	`conf`	Novel Fault-Tolerant Techniques for High Capacity RAMs. PRDC Chih-Hsien Hsu, Shyue-Kung Lu, Sy-Yen Kuo
2000	—	`conf`	A Testable/Fault Tolerant FFT Processor Design. Asian Test Symposium Shyue-Kung Lu, Jen-Sheng Shih, Cheng-Wen Wu
2000	C	`conf`	Built-in self-test and fault diagnosis for lookup table FPGAs. ISCAS Shyue-Kung Lu, Jen-Sheng Shih, Cheng-Wen Wu
2000	J	`jnl`	Testing Configurable LUT-Based FPGAs. J. Inf. Sci. Eng. Shyue-Kung Lu, Jen-Sheng Shih
1999	—	`conf`	A novel approach to testing LUT-based FPGAs. ISCAS (1) Shyue-Kung Lu, Cheng-Wen Wu
1999	—	`conf`	Defect Level Prediction Using Multi-Model Fault Coverage. Asian Test Symposium Shyue-Kung Lu, Tsung-Ying Lee, Cheng-Wen Wu
1997	J	`jnl`	Fault-Tolerant Interleaved Memory Systems with Two-Level Redundancy. IEEE Trans. Computers Shyue-Kung Lu, Sy-Yen Kuo, Cheng-Wen Wu
1996	J	`jnl`	Cell delay fault testing for iterative logic arrays. J. Electron. Test. Shyue-Kung Lu, Cheng-Wen Wu, Ruei-Zong Hwang
1995	J	`jnl`	C-testable design techniques for iterative logic arrays. IEEE Trans. Very Large Scale Integr. Syst. Shyue-Kung Lu, Jen-Chuan Wang, Cheng-Wen Wu
1991	C	`conf`	Designing Self-Testable Cellular Arrays. ICCD Cheng-Wen Wu, Shyue-Kung Lu