Shyh-Jye Jou

161 papers A 10C 33Misc 2Journal 58Unranked 57
YearRankTypeTitle / Venue / Authors
2025 — conf
A CIM Crossbar Array Data Mapping Methodology for Unstructured Sparse CNN.
AICAS
Yan-Lin Hung, Ping-Han Liu, Zun-Sheng Wu, Bo-Cheng Lai, Shyh-Jye Jou
2025 C conf
A Deep Learning Accelerator for Modified YOLOv7-tiny with Shortcut-Aware Layer Fusion.
ISCAS
Wei-En Huang, Yi-Shan Huang, Shyh-Jye Jou
2025 J jnl
Synchronization and Channel Estimation Design for Multi-Stream MIMO System in Sub-Terahertz Channel Model.
IEEE Open J. Circuits Syst.
Chung-Lun Tu, Chen-Yuan Tseng, Wei-Che Lee, Kang-Lun Chiu, Pei-Yun Tsai, Shyh-Jye Jou
2024 C conf
A 128 Gb/s LDPC Decoder Using Partial Syndrome-based Dynamic Decoding Scheme for Terahertz Wireless Multi-Media Networks.
ISCAS
Tsung-Han Wu, Ching Liang Yeh, Yi-Shan Huang, Shyh-Jye Jou
2024 A conf
A Multi-Bit Near-RRAM based Computing Macro with Highly Computing Parallelism for CNN Application.
DATE
Kuan-Chih Lin, Hao Zuo, Hsiang-Yu Wang, Yuan-Ping Huang, Ci-Hao Wu, Yan-Cheng Guo, Shyh-Jye Jou, Tuo-Hung Hou, Tian-Sheuan Chang
2024 C conf
Channel Estimation and Equalization Design with SNR Decision Based Universal Threshold for Sub-THz Single Carrier Baseband Receiver.
ISCAS
Feng-Ju Liao, Chung-Lun Tu, Shyh-Jye Jou
2024 — conf
Efficient Analog Layout Generation for In-RRAM Computing Circuits via Area and Wire Optimization.
MWSCAS
Bo-Han Li, Kuan-Chih Lin, Hao Zuo, Po-Cheng Pan, Hung-Ming Chen, Shyh-Jye Jou, Chien-Nan Jimmy Liu, Bo-Cheng Lai
2024 C conf
Online Self-Adaptive Estimation and Compensation Design for DC Voltage Offset, Frequency-Independent, and Frequency-Dependent IQ Mismatch in Sub-THz Digital Baseband Transceiver.
ISCAS
Chia-Jung Lee, Chung-Lun Tu, Shyh-Jye Jou
2023 J jnl
A Digital Frequency-Dependent I/Q Imbalance and Group Delay Estimation and Compensation Modules for mmWave Single Carrier Baseband Transceivers.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Chih-Wei Jen, Hung-Chih Liu, Zheng-Chun Huang, Nai-Cheng Xue, Shyh-Jye Jou
2023 J jnl
Low Routing Complexity Multiframe Pipelined LDPC Decoder Based on a Novel Pseudo Marginalized Min-Sum Algorithm for High Throughput Applications.
IEEE Trans. Very Large Scale Integr. Syst.
Henry Lopez Davila, Tsung-Han Wu, Shyh-Jye Jou, Sau-Gee Chen, Pei-Yun Tsai
2023 C conf
Offline and Time-variant EVD-based Closed-loop Digital Predistortion Design for Sub-THz Power Amplifier Array in Basedband Transmitter.
ISCAS
Chung-Lun Tu, Chin-Ming Chang, Shyh-Jye Jou
2023 — conf
On Automating Finger-Cap Array Synthesis with Optimal Parasitic Matching for Custom SAR ADC.
ASP-DAC
Cheng-Yu Chiang, Chia-Lin Hu, Mark Po-Hung Lin, Yu-Szu Chung, Shyh-Jye Jou, Jieh-Tsorng Wu, Shiuh-Hua Wood Chiang, Chien-Nan Jimmy Liu, Hung-Ming Chen
2022 J jnl
A 14 μJ/Decision Keyword-Spotting Accelerator With In-SRAMComputing and On-Chip Learning for Customization.
IEEE Trans. Very Large Scale Integr. Syst.
Yu-Hsiang Chiang, Tian-Sheuan Chang, Shyh-Jye Jou
2022 J jnl
A 14uJ/Decision Keyword Spotting Accelerator with In-SRAM-Computing and On Chip Learning for Customization.
CoRR
Yu-Hsiang Chiang, Tian-Sheuan Chang, Shyh-Jye Jou
2022 — conf
An 1-bit by 1-bit High Parallelism In-RRAM Macro with Co-Training Mechanism for DCNN Applications.
VLSI-DAT
Chi Liu, Shao-Tzu Li, Tong-Lin Pan, Cheng-En Ni, Yun Sung, Chia-Lin Hu, Kang-Yu Chang, Tuo-Hung Hou, Tian-Sheuan Chang, Shyh-Jye Jou
2022 C conf
Compressive Sensing Based Hardware Design for Channel Estimation of Wideband Millimeter Wave Hybrid MIMO System.
ISCAS
Chung-Lun Tu, Tse-Yuan Lin, Kang-Lun Chiu, Shyh-Jye Jou, Pei-Yun Tsai
2022 A conf
DASC: A DRAM Data Mapping Methodology for Sparse Convolutional Neural Networks.
DATE
Bo-Cheng Lai, Tzu-Chieh Chiang, Po-Shen Kuo, Wan-Ching Wang, Yan-Lin Hung, Hung-Ming Chen, Chien-Nan Liu, Shyh-Jye Jou
2022 C conf
Design of a mmWave Digital Baseband Receiver Integrated with WOLA-CP-OFDM Technique.
ISCAS
Kang-Lun Chiu, Hsun-Wei Chan, Hsuan-Ping Chiu, Chun-Yi Liu, Chih-Wei Jen, Shyh-Jye Jou
2022 J jnl
Hardware-Robust In-RRAM-Computing for Object Detection.
CoRR
Yu-Hsiang Chiang, Cheng-En Ni, Yun Sung, Tuo-Hung Hou, Tian-Sheuan Chang, Shyh-Jye Jou
2022 J jnl
Hardware-Robust In-RRAM-Computing for Object Detection.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Yu-Hsiang Chiang, Cheng-En Ni, Yun Sung, Tuo-Hung Hou, Tian-Sheuan Chang, Shyh-Jye Jou
2022 J jnl
Joint Digital Online Compensation of TX and RX Time-Varying I/Q Mismatch and DC-Offset in mmWave Transceiver System.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hung-Chih Liu, Zheng-Chun Huang, Ngoc-Giang Doan, Chih-Wei Jen, Shyh-Jye Jou
2022 C conf
Low-Complexity Pseudo Direct Learning Digital Pre-Distortion Architecture for Nonlinearity and Memory Effect of Power Amplifier in mmWave Baseband Transmitter.
ISCAS
Shen-Zhe Lu, Nai-Cheng Xue, Hung-Chih Liu, Chih-Wei Jen, Shyh-Jye Jou
2022 — conf
On Optimizing Capacitor Array Design for Advanced Node SAR ADC.
SMACD
Cheng-Yu Chiang, Chia-Lin Hu, Kang-Yu Chang, Mark Po-Hung Lin, Shyh-Jye Jou, Hung-Yu Chen, Chien-Nan Jimmy Liu, Hung-Ming Chen
2021 J jnl
A Digital Two-Stage Phase Noise Compensation and rCFO/rSCO Tracking Module for mmW Single Carrier Systems.
IEEE Trans. Very Large Scale Integr. Syst.
Hsun-Wei Chan, Wei-Che Lee, Kang-Lun Chiu, Chih-Wei Jen, Shyh-Jye Jou
2021 C conf
A Low-Jitter ADPLL with Adaptive High-Order Loop Filter and Fine Grain Varactor Based DCO.
ISCAS
Chia-Chen Chang, Yu-Tung Chin, Hossameldin A. Ibrahim, Kang-Yu Chang, Shyh-Jye Jou
2021 — conf
A Reconfigurable In-SRAM Computing Architecture for DCNN Applications.
VLSI-DAT
Yu-Hsien Lin, Chi Liu, Chia-Lin Hu, Kang-Yu Chang, Jia-Yin Chen, Shyh-Jye Jou
2021 — conf
On Reconfiguring Memory-Centric AI Edge Devices for CIM.
ISOCC
Hung-Ming Chen, Cheng-En Ni, Kang-Yu Chang, Tzu-Chieh Chiang, Shih-Han Chang, Cheng-Yu Chiang, Bo-Cheng Lai, Chien-Nan Liu, Shyh-Jye Jou
2020 — conf
A 16/64 QAM Baseband SoC for mm-Wave Transceiver with Self-Healing for FD/FI IQ Mismatch, LO Leakage and CFO/SCO/PNC.
A-SSCC
Hung-Chih Liu, Hsun-Wei Chan, Henry Lopez Davila, Kang-Lun Chiu, Chih-Wei Jen, Ngoc-Giang Doan, Zheng-Chun Huang, Hsin-Ting Chang, Nien-Hsiang Chang, Pei-Yun Tsai, Yen-Cheng Kuan, Shyh-Jye Jou
2020 J jnl
A 75-Gb/s/mm
IEEE Trans. Very Large Scale Integr. Syst.
Henry Lopez Davila, Hsun-Wei Chan, Kang-Lun Chiu, Pei-Yun Tsai, Shyh-Jye Jou
2020 J jnl
Design of Downlink Synchronization for Millimeter Wave Cellular System Based on Multipath Division Multiple Access.
IEEE Trans. Circuits Syst. I Regul. Pap.
Kang-Lun Chiu, Pai-Hsiang Shen, Bing-Ru Lin, Wei-Han Hsiao, Shyh-Jye Jou, Chia-Chi Huang
2020 C conf
Digital Self-Healing using Smart Sensing Technique for IQ Mismatch and LO Leakage against Non-Flat Path Response in mmWave Communication System.
ISCAS
Ngoc-Giang Doan, Hung-Chih Liu, Chih-Wei Jen, Shyh-Jye Jou
2020 A conf
On EDA Solutions for Reconfigurable Memory-Centric AI Edge Applications.
ICCAD
Hung-Ming Chen, Chia-Lin Hu, Kang-Yu Chang, Alexandra Küster, Yu-Hsien Lin, Po-Shen Kuo, Wei-Tung Chao, Bo-Cheng Lai, Chien-Nan Liu, Shyh-Jye Jou
2019 — conf
A 50 Gb/s Adaptive ADFE with SNR Based Power Management for 2-PAM Systems.
VLSI-DAT
Chee-Kit Ng, Yu-Chun Lin, Shyh-Jye Jou
2019 C conf
A 50 Gb/s Adaptive Dual Data-Paths NS-EICL ADFE with 50 Parallelisms for 2-PAM Systems.
ISCAS
Chee-Kit Ng, Kang-Lun Chiu, Yu-Chun Lin, Shyh-Jye Jou
2019 — conf
A Millimeter Wave Digital CMOS Baseband Transceiver for Wireless LAN Applications.
A-SSCC
Kang-Lun Chiu, Hsun-Wei Chan, Wei-Che Lee, Chang-Ting Wu, Henry Lopez Davila, Hung-Chih Liu, Meng-Yuan Huang, Chun-Yi Liu, Tsai-Hua Lee, Hsin-Ting Chang, Chih-Wei Jen, Nien-Hsiang Chang, Pei-Yun Tsai, Yen-Cheng Kuan, Shyh-Jye Jou
2019 — conf
Sub-ns Access Sub-mW/GHz 32 Kb SRAM with 0.45 V Cross-Point-5T Cell and Built-in Y_ Line.
A-SSCC
C. Y. He, K. H. Tang, T. S. Chen, K. Y. Chang, C. H. Lin, K. Sato, Shyh-Jye Jou, P. H. Chen, H. M. Chen, B. D. Rong, K. Itoh
2019 — conf
Synthesizable Injection-Locked Phase-Locked Loop with Multiphase Interlocking Digitally Controlled Oscillator Arrays.
ASICON
Yu-Cheng Su, Kang-Yu Chang, Yu-Tung Chin, Chia-Wen Chang, Shyh-Jye Jou
2018 C conf
A 40Gb/s All-Digital Adaptive Noise-Suppression Feed-Forward Filter and Adaptive Decision Feedback Equalizer with 40 parallelisms for 2-PAM Systems.
ISCAS
Chee-Kit Ng, Yu-Chun Lin, Wei-Chang Liu, Chih-Feng Wu, Shyh-Jye Jou
2018 C conf
Digital Self-Interference Cancellation for OFDM Full-Duplex Transmission in 60 GHz Band.
ISCAS
Chih-Wei Jen, Hung-Wei Yang, Hsun-Wei Chan, Hung-Chih Liu, Henry Lopez Davila, Chun-Yi Liu, Shyh-Jye Jou
2017 J jnl
A MMSE Joint Feedback Feed-forward Equalizer for FBMC-OQAM Baseband Receiver in the 60 GHz Band.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Chun-Yi Liu, Edmund Wen Jen Leong, Chang-Ting Wu, Meng-Siou Sie, Henry Lopez Davila, Chih-Wei Jen, Shyh-Jye Jou
2017 — conf
A pseudo MMSE linear equalizer for 60GHz single carrier baseband receiver.
ASICON
Hsun-Wei Chan, Chang-Ting Wu, Chih-Wei Jen, Chun-Yi Liu, Wei-Che Lee, Shyh-Jye Jou
2017 J jnl
Dual-Mode All-Digital Baseband Receiver With a Feed-Forward and Shared-Memory Architecture for Dual-Standard Over 60 GHz NLOS Channel.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chun-Yi Liu, Meng-Siou Sie, Edmund Wen Jen Leong, Yu-Cheng Yao, Chih-Wei Jen, Wei-Chang Liu, Chih-Feng Wu, Shyh-Jye Jou
2017 C conf
Residual sampling clocking offset estimation and compensation for FBMC-OQAM baseband receiver in the 60 GHz band.
ISCAS
Chun-Yi Liu, Yu-Cheng Yao, Meng-Siou Sie, Edmund Wen Jen Leong, Henry Lopez Davila, Chih-Wei Jen, Shyh-Jye Jou
2016 J jnl
A Systematic ANSI S1.11 Filter Bank Specification Relaxation and Its Efficient Multirate Architecture for Hearing-Aid Systems.
IEEE ACM Trans. Audio Speech Lang. Process.
Cheng-Yen Yang, Chih-Wei Liu, Shyh-Jye Jou
2016 J jnl
A Varactor-Based All-Digital Multi-Phase PLL with Random-Sampling Spur Suppression Techniques.
IEICE Trans. Electron.
Chia-Wen Chang, Kai-Yu Lo, Hossameldin A. Ibrahim, Ming-Chiuan Su, Yuan-Hua Chu, Shyh-Jye Jou
2016 C conf
A memory access reordering polyphase network for 60 GHz FBMC-OQAM baseband receiver.
ISCAS
Chun-Yi Liu, Meng-Siou Sie, Edmund Wen Jen Leong, Yu-Cheng Yao, Chih-Wei Jen, Shyh-Jye Jou
2016 C conf
A subthreshold SRAM with embedded data-aware write-assist and adaptive data-aware keeper.
ISCAS
Yi-Wei Chiu, Yu-Hao Hu, Jun-Kai Zhao, Shyh-Jye Jou, Ching-Te Chuang
2016 J jnl
An 8X-Parallelism Memory Access Reordering Polyphase Network for 60 GHz FBMC-OQAM Baseband Receiver.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chun-Yi Liu, Meng-Siou Sie, Edmund Wen Jen Leong, Yu-Cheng Yao, Henry Lopez Davila, Chih-Wei Jen, Wei-Chang Liu, Shyh-Jye Jou
2016 J jnl
Dynamic Error-Compensated Fixed-Width Booth Multiplier Based on Conditional-Probability of Input Series.
Circuits Syst. Signal Process.
Wen-Quan He, Yuan-Ho Chen, Shyh-Jye Jou
2016 Misc conf
Error-resilient sequential cells with successive time borrowing for stochastic computing.
ICASSP
Wei-Chang Liu, Ching-Da Chan, Shuo-An Huang, Chi-Wei Lo, Chia-Hsiang Yang, Shyh-Jye Jou
2016 J jnl
Golay-Correlator Window-Based Noise Cancellation Equalization Technique for 60-GHz Wireless OFDM/SC Receiver.
IEEE Trans. Very Large Scale Integr. Syst.
Chih-Feng Wu, Wei-Chang Liu, Chia-Chun Tsui, Chun-Yi Liu, Meng-Siou Sie, Shyh-Jye Jou
2016 — conf
Interference measurement and analysis of full-duplex wireless system in 60 GHz band.
APCCAS
Hung-Wei Yang, Yongyu He, Chih-Wei Jen, Chun-Yi Liu, Shyh-Jye Jou, Xuefeng Yin, Meng Ma, Bingli Jiao
2015 J jnl
A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist.
IEEE Trans. Very Large Scale Integr. Syst.
Chien-Yu Lu, Ching-Te Chuang, Shyh-Jye Jou, Ming-Hsien Tu, Ya-Ping Wu, Chung-Ping Huang, Paul-Sen Kan, Huan-Shun Huang, Kuen-Di Lee, Yung-Shin Kao
2015 J jnl
A 10-Gb/s, 1.24 pJ/bit, Burst-Mode Clock and Data Recovery With Jitter Suppression.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ming-Chiuan Su, Wei-Zen Chen, Pei-Si Wu, Yu-Hsian Chen, Chao-Cheng Lee, Shyh-Jye Jou
2015 C conf
A 28nm 36kb high speed 6T SRAM with source follower PMOS read and bit-line under-drive.
ISCAS
Chi-Hao Hong, Yi-Wei Chiu, Jun-Kai Zhao, Shyh-Jye Jou, Wen-Tai Wang, Reed Lee
2015 — conf
A 3.52 Gb/s mmWave baseband with delayed decision feedback sequence estimation in 40 nm.
A-SSCC
Nicholas Preyss, Christian Senning, Andreas Burg, Wei-Chang Liu, Chun-Yi Liu, Shyh-Jye Jou
2015 — conf
A 802.15.3c/802.11ad compliant 24 Gb/s FFT processor for 60 GHz communication systems.
SoCC
Henry Lopez Davila, Chun-Yi Liu, Wei-Chang Liu, Shen-Jui Huang, Shyh-Jye Jou, Sau-Gee Chen
2015 — conf
A 802.15.3c/802.11ad dual mode phase noise cancellation for 60 GHz communication systems.
VLSI-DAT
Liang-Yu Huang, Chia-Yi Wu, Chun-Yi Liu, Wei-Chang Liu, Chih-Feng Wu, Shyh-Jye Jou
2015 J jnl
A Low-Jitter Cell-Based Digitally Controlled Oscillator With Differential Multiphase Outputs.
IEEE Trans. Very Large Scale Integr. Syst.
Ming-Chiuan Su, Shyh-Jye Jou, Wei-Zen Chen
2015 J jnl
A Near-Threshold Cell-Based All-Digital PLL with Hierarchical Band-Selection G-DCO for Fast Lock-In and Low-Power Applications.
IEICE Trans. Electron.
Chia-Wen Chang, Yuan-Hua Chu, Shyh-Jye Jou
2015 J jnl
All-Digital Synchronization for SC/OFDM Mode of IEEE 802.15.3c and IEEE 802.11ad.
IEEE Trans. Circuits Syst. I Regul. Pap.
Wei-Chang Liu, Ting-Chen Wei, Ya-Shiue Huang, Ching-Da Chan, Shyh-Jye Jou
2015 — conf
Full-digital high throughput design of adaptive decision feedback equalizers using coefficient-lookahead.
ASICON
Wen-Quan He, Yu-Chun Lin, Jui-Yi Hung, Shyh-Jye Jou
2015 — conf
Gb/s prototyping of 60GHz indoor wireless SC/OFDM transmitter and receiver on FPGA demo system.
ICCE-TW
Pranav Arya, Liang-Yu Huang, Wei-Chang Liu, Hsin-Ting Chang, Chih-Wei Jen, Chih-Feng Wu, Shyh-Jye Jou
2015 J jnl
High-Accuracy Fixed-Width Booth Multipliers Based on Probability and Simulation.
IEEE Trans. Circuits Syst. I Regul. Pap.
Wen-Quan He, Yuan-Ho Chen, Shyh-Jye Jou
2014 J jnl
40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yi-Wei Chiu, Yu-Hao Hu, Ming-Hsien Tu, Jun-Kai Zhao, Yuan-Hua Chu, Shyh-Jye Jou, Ching-Te Chuang
2014 J jnl
A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist.
IEEE Trans. Circuits Syst. I Regul. Pap.
Nan-Chun Lien, Li-Wei Chu, Chien-Hen Chen, Hao-I Yang, Ming-Hsien Tu, Paul-Sen Kan, Yong-Jyun Hu, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang
2014 — conf
A 40nm 256kb 6T SRAM with threshold power-gating, low-swing global read bit-line, and charge-sharing write with Vtrip-tracking and negative source-line write-assists.
SoCC
Chao-Kuei Chung, Chien-Yu Lu, Zhi-Hao Chang, Shyh-Jye Jou, Ching-Te Chuang, Ming-Hsien Tu, Yu-Hsian Chen, Yong-Jyun Hu, Paul-Sen Kan, Huan-Shun Huang, Kuen-Di Lee, Yung-Shin Kao
2014 — conf
A low-power charge sharing hierarchical bitline and voltage-latched sense amplifier for SRAM macro in 28 nm CMOS technology.
SoCC
Chi-Hao Hong, Yi-Wei Chiu, Jun-Kai Zhao, Shyh-Jye Jou, Wen-Tai Wang, Reed Lee
2014 C conf
An IEEE 802.15.3c/802.11ad compliant SC/OFDM dual-mode baseband receiver for 60 GHz Band.
ISCAS
Wei-Chang Liu, Fu-Chun Yeh, Chia-Yi Wu, Ting-Chen Wei, Ya-Shiue Huang, Shen-Jui Huang, Ching-Da Chan, Shyh-Jye Jou, Sau-Gee Chen
2014 Misc conf
An efficient 18-band quasi-ANSI 1/3-octave filter bank using re-sampling method for digital hearing aids.
ICASSP
Cheng-Yen Yang, Chih-Wei Liu, Shyh-Jye Jou
2014 C conf
An ultra-low voltage hearing aid chip using variable-latency design technique.
ISCAS
Kuo-Chiang Chang, Shien-Chun Luo, Ching-Ji Huang, Chih-Wei Liu, Yuan-Hua Chu, Shyh-Jye Jou
2014 J jnl
Analysis and implementation of low-power perceptual multiband noise reduction for the hearing aids application.
IET Circuits Devices Syst.
Cheng-Wen Wei, Cheng-Chun Tsai, FanJiang Yi, Tian-Sheuan Chang, Shyh-Jye Jou
2014 J jnl
Blind ICA detection based on second-order cone programming for MC-CDMA systems.
EURASIP J. Adv. Signal Process.
Chih-Wei Jen, Shyh-Jye Jou
2014 J jnl
Continuous-flow Parallel Bit-Reversal Circuit for MDF and MDC FFT Architectures.
IEEE Trans. Circuits Syst. I Regul. Pap.
Sau-Gee Chen, Shen-Jui Huang, Mario Garrido, Shyh-Jye Jou
2014 J jnl
Correction to "Low complexity formant estimation adaptive feedback cancellation for hearing aids using pitch based processing".
IEEE ACM Trans. Audio Speech Lang. Process.
Yi FanChiang, Cheng-Wen Wei, Yi-Le Meng, Yu-Wen Lin, Shyh-Jye Jou, Tian-Sheuan Chang
2014 J jnl
Low Complexity Formant Estimation Adaptive Feedback Cancellation for Hearing Aids Using Pitch Based Processing.
IEEE ACM Trans. Audio Speech Lang. Process.
Yi FanChiang, Cheng-Wen Wei, Yi-Le Meng, Yu-Wen Lin, Shyh-Jye Jou, Tian-Sheuan Chang
2014 J jnl
Neuromorphic Pitch Based Noise Reduction for Monosyllable Hearing Aid System Application.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yu-Jui Chen, Cheng-Wen Wei, Yi FanChiang, Yi-Le Meng, Yi-Cheng Huang, Shyh-Jye Jou
2013 — conf
A 10Gbps, 1.24pJ/bit, burst-mode clock and data recovery with jitter suppression.
CICC
Ming-Chiuan Su, Wei-Zen Chen, Pei-Si Wu, Yu-Hsian Chen, Chao-Cheng Lee, Shyh-Jye Jou
2013 A conf
A 40 nm 0.32 V 3.5 MHz 11T single-ended bit-interleaving subthreshold SRAM with data-aware write-assist.
ISLPED
Yi-Wei Chiu, Yu-Hao Hu, Ming-Hsien Tu, Jun-Kai Zhao, Shyh-Jye Jou, Ching-Te Chuang
2013 — conf
A 40nm 1.0Mb 6T pipeline SRAM with digital-based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS tracking and Adaptive Voltage Detector for boosting control.
SoCC
Wei-Nan Liao, Nan-Chun Lien, Chi-Shin Chang, Li-Wei Chu, Hao-I Yang, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang, Ming-Hsien Tu, Huan-Shun Huang, Jian-Hao Wang, Paul-Sen Kan, Yong-Jyun Hu
2013 C conf
A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist.
ISCAS
Chi-Shin Chang, Hao-I Yang, Wei-Nan Liao, Yi-Wei Lin, Nan-Chun Lien, Chien-Hen Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Ming-Hsien Tu, Huan-Shun Huang, Yong-Jyun Hu, Paul-Sen Kan, Cheng-Yo Cheng, Wei-Chang Wang, Jian-Hao Wang, Kuen-Di Lee, Chia-Cheng Chen, Wei-Chiang Shih
2013 J jnl
A Digital Golay-MPIC Time Domain Equalizer for SC/OFDM Dual-Modes at 60 GHz Band.
IEEE Trans. Circuits Syst. I Regul. Pap.
Wei-Chang Liu, Fu-Chun Yeh, Ting-Chen Wei, Ching-Da Chan, Shyh-Jye Jou
2013 J jnl
A Low-Overhead Interference Canceller for High-Mobility STBC-OFDM Systems.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hsiao-Yun Chen, Wei-Kai Chang, Shyh-Jye Jou
2013 J jnl
A Low-Power Level-Converting Double-Edge-Triggered Flip-Flop Design.
IEICE Trans. Electron.
Li-Rong Wang, Kai-Yu Lo, Shyh-Jye Jou
2013 C conf
A SC/HSI dual-mode baseband receiver with frequency-domain equalizer for IEEE 802.15.3c.
ISCAS
Wei-Chang Liu, Fu-Chun Yeh, Ting-Chen Wei, Ya-Shiue Huang, Tai-Yang Liu, Shen-Jui Huang, Ching-Da Chan, Shyh-Jye Jou, Sau-Gee Chen
2013 — conf
A pitch based VAD adopting quasi-ANSI 1/3 octave filter bank with 11.3 ms latency for monosyllable hearing aids.
SiPS
Yi-Cheng Huang, Fan-Chiang Yi, Shyh-Jye Jou
2013 — conf
Power and area reduction in multi-stage addition using operand segmentation.
VLSI-DAT
Ching-Da Chan, Wei-Chang Liu, Chia-Hsiang Yang, Shyh-Jye Jou
2013 J jnl
STBC-OFDM Downlink Baseband Receiver for Mobile WMAN.
IEEE Trans. Very Large Scale Integr. Syst.
Hsiao-Yun Chen, Jyun-Nan Lin, Hsiang-Sheng Hu, Shyh-Jye Jou
2013 — conf
Spatial-cue-based multi-band binaural noise reduction for hearing aids.
SiPS
Cheng-Yen Yang, Wen-Sheng Chou, Kuo-Chiang Chang, Chih-Wei Liu, Tai-Shih Chi, Shyh-Jye Jou
2012 J jnl
A 0.33-V, 500-kHz, 3.94-µW 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist.
IEEE Trans. Circuits Syst. II Express Briefs
Chien-Yu Lu, Ming-Hsien Tu, Hao-I Yang, Ya-Ping Wu, Huan-Shun Huang, Yuh-Jiun Lin, Kuen-Di Lee, Yung-Shin Kao, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang
2012 J jnl
A 5.79-Gb/s Energy-Efficient Multirate LDPC Codec Chip for IEEE 802.15.3c Applications.
IEEE J. Solid State Circuits
Shao-Wei Yen, Shiang-Yu Hung, Chih-Lung Chen, Hsie-Chia Chang, Shyh-Jye Jou, Chen-Yi Lee
2012 — conf
A 80-uW 2-Mb/s transceiver for human body channel binaural communication.
BioCAS
Jhih-Cing Sun, Jou-Ling Chen, Yi-Hung Shen, Shiu-Chain You, Shyh-Jye Jou, Tzu-Hsien Sang
2012 J jnl
A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing.
IEEE J. Solid State Circuits
Ming-Hsien Tu, Jihi-Yu Lin, Ming-Chien Tsai, Chien-Yu Lu, Yuh-Jiun Lin, Meng-Hsueh Wang, Huan-Shun Huang, Kuen-Di Lee, Wei-Chiang Shih, Shyh-Jye Jou, Ching-Te Chuang
2012 — conf
A low-power body-channel communication system for binaural hearing aids.
BioCAS
Jou-Ling Chen, Jhih-Cing Sun, Yi-Hung Shen, Tzu-Hsien Sang, Tian-Sheuan Chang, Shyh-Jye Jou
2012 — conf
An all-digital Read Stability and Write Margin characterization scheme for CMOS 6T SRAM array.
VLSI-DAT
Yi-Wei Lin, Ming-Chien Tsai, Hao-I Yang, Geng-Cing Lin, Shao-Cheng Wang, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang, Nan-Chun Lien, Kuen-Di Lee, Wei-Chiang Shih
2012 C conf
An all-digital bit transistor characterization scheme for CMOS 6T SRAM array.
ISCAS
Geng-Cing Lin, Shao-Cheng Wang, Yi-Wei Lin, Ming-Chien Tsai, Ching-Te Chuang, Shyh-Jye Jou, Nan-Chun Lien, Wei-Chiang Shih, Kuen-Di Lee, Jyun-Kai Chu
2012 — conf
Design and implementation of dynamic Word-Line pulse write margin monitor for SRAM.
APCCAS
Shao-Cheng Wang, Geng-Cing Lin, Yi-Wei Lin, Ming-Chien Tsai, Yi-Wei Chiu, Shyh-Jye Jou, Ching-Te Chuang, Nan-Chun Lien, Wei-Chiang Shih, Kuen-Di Lee, Jyun-Kai Chu
2012 — conf
Embedded SRAM ring oscillator for in-situ measurement of NBTI and PBTI degradation in CMOS 6T SRAM array.
VLSI-DAT
Ming-Chien Tsai, Yi-Wei Lin, Hao-I Yang, Ming-Hsien Tu, Wei-Chiang Shih, Nan-Chun Lien, Kuen-Di Lee, Shyh-Jye Jou, Ching-Te Chuang, Wei Hwang
2012 J jnl
High throughput concurrent lookahead adaptive decision feedback equaliser.
IET Circuits Devices Syst.
Yu-Chun Lin, Shyh-Jye Jou, Muh-Tian Shiue
2012 C conf
High-performance 0.6V VMIN 55nm 1.0Mb 6T SRAM with adaptive BL bleeder.
ISCAS
Hao-I Yang, Yi-Wei Lin, Mao-Chih Hsia, Geng-Cing Lin, Chi-Shin Chang, Yin-Nien Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Nan-Chun Lien, Hung-Yu Li, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, Chih-Chiang Hsu
2012 J jnl
Sub µW Noise Reduction for CIC Hearing Aids.
IEEE Trans. Very Large Scale Integr. Syst.
Cheng-Wen Wei, Sheng-Jie Su, Tian-Sheuan Chang, Shyh-Jye Jou
2012 A conf
Testing strategies for a 9T sub-threshold SRAM.
ITC
Hao-Yu Yang, Chen-Wei Lin, Hung-Hsin Chen, Mango Chia-Tso Chao, Ming-Hsien Tu, Shyh-Jye Jou, Ching-Te Chuang
2012 — conf
Welcome from the general chairs.
VLSI-DAT
Michel Brillouët, Shyh-Jye Jou, C. Patrick Yue
2011 — conf
0.5 VDD digitally controlled oscillators design with compensation techniques for PVT variations.
ASICON
Chia-Wen Chang, Shyh-Jye Jou, Yuan-Hua Chu
2011 A conf
8T single-ended sub-threshold SRAM with cross-point data-aware write operation.
ISLPED
Yi-Wei Chiu, Jihi-Yu Lin, Ming-Hsien Tu, Shyh-Jye Jou, Ching-Te Chuang
2011 — conf
A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control.
SoCC
Hao-I Yang, Shih-Chi Yang, Mao-Chih Hsia, Yung-Wei Lin, Yi-Wei Lin, Chien-Hen Chen, Chi-Shin Chang, Geng-Cing Lin, Yin-Nien Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Nan-Chun Lien, Hung-Yu Li, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, Chih-Chiang Hsu
2011 — conf
Digitally-controlled cell-based oscillator with multi-phase differential outputs.
ASICON
Ming-Chiuan Su, Shyh-Jye Jou
2011 C conf
Low power InfomaxICA with compensation strategy for binaural hearing-aid.
ISCAS
Fan-Chiang Yi, Ching-Wen Huang, Tai-Shih Chi, Shyh-Jye Jou
2011 J jnl
Well-Structured Modified Booth Multiplier and Its Application to Reconfigurable MAC Design.
IEICE Trans. Electron.
Li-Rong Wang, Ming-Hsien Tu, Shyh-Jye Jou, Chung-Len Lee
2010 J jnl
A Robust Channel Estimator for High-Mobility STBC-OFDM Systems.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hsiao-Yun Chen, Meng-Lin Ku, Shyh-Jye Jou, Chia-Chi Huang
2010 — conf
Perceptual multiband spectral subtraction for noise reduction in hearing aids.
APCCAS
Cheng-Wen Wei, Cheng-Chun Tsai, Tian-Sheuan Chang, Shyh-Jye Jou
2010 J jnl
Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-Assist.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ming-Hsien Tu, Jihi-Yu Lin, Ming-Chien Tsai, Shyh-Jye Jou, Ching-Te Chuang
2009 C conf
10Gbps Decision Feedback Equalizer with Dynamic Lookahead Decision Loop.
ISCAS
Yu-Chun Lin, Muh-Tian Shiue, Shyh-Jye Jou
2009 — conf
A 0.92mm
CICC
Shao-Wei Yen, Ming-Chih Hu, Chin-Lung Chen, Hsie-Chia Chang, Shyh-Jye Jou, Chen-Yi Lee
2009 — conf
Asymmetrical Write-assist for single-ended SRAM operation.
SoCC
Jihi-Yu Lin, Ming-Hsien Tu, Ming-Chien Tsai, Shyh-Jye Jou, Ching-Te Chuang
2009 J jnl
Design of a Multimode QC-LDPC Decoder Based on Shift-Routing Network.
IEEE Trans. Circuits Syst. II Express Briefs
Chih-Hao Liu, Chien-Ching Lin, Shao-Wei Yen, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee, Yar-Sun Hsu, Shyh-Jye Jou
2009 J jnl
Low complexity synchronization design of an OFDM receiver for DVB-T/H.
IEEE Trans. Consumer Electron.
Ting-Chen Wei, Wei-Chang Liu, Chi-Yao Tseng, Shyh-Jye Jou
2008 — conf
A 28mW OFDM baseband receiver chip for DVB-T/H with all digital synchronization.
CICC
Ting-Chen Wei, Wei-Chang Liu, Chi-Yao Tseng, Syu-Siang Long, Shyh-Jye Jou, Muh-Tian Shiue
2008 J jnl
A jointed mode detection and symbol detection scheme for DVB-T.
IEEE Trans. Consumer Electron.
Wei-Ting Chen, Wei-Chang Liu, Shyh-Jye Jou
2008 C conf
A reconfigurable MAC architecture implemented with mixed-Vt standard cell library.
ISCAS
Li-Rong Wang, Yi-Wei Chiu, Chia-Lin Hu, Ming-Hsien Tu, Shyh-Jye Jou, Chung-Len Lee
2008 J jnl
An LDPC Decoder Chip Based on Self-Routing Network for IEEE 802.16e Applications.
IEEE J. Solid State Circuits
Chih-Hao Liu, Shau-Wei Yen, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee, Yar-Sun Hsu, Shyh-Jye Jou
2008 J jnl
Introduction to the Special Section on the 2007 Asian Solid-State Circuits Conference (A-SSCC'07).
IEEE J. Solid State Circuits
Nicky Lu, Shyh-Jye Jou
2008 C conf
Symbol and carrier frequency offset synchronization for IEEE802.16e.
ISCAS
Jyun-Nan Lin, Hsiao-Yun Chen, Ting-Chen Wei, Shyh-Jye Jou
2007 C conf
Blind Mode/GI Detection and Coarse Symbol Synchronization for DVB-T/H.
ISCAS
Wei-Chang Liu, Ting-Chen Wei, Shyh-Jye Jou
2007 — conf
Concurrent Digital Adaptive Decision Feedback Equalizer for 10GBase-LX4 Ethernet System.
CICC
Chi-Shiung Lin, Yu-Chun Lin, Shyh-Jye Jou, Mun-Tian Shiou
2007 J jnl
Design and analysis of digital data recovery circuits using oversampling.
IET Circuits Devices Syst.
Shyh-Jye Jou, Chih-Hsien Lin, Yen-Hung Chen, Zheng-Hong Li
2007 — conf
Mixed-VTH (MVT) CMOS circuit design for low power cell libraries.
SoCC
Jiun-Yi Lin, Li-Rong Wang, Chia-Lin Hu, Shyh-Jye Jou
2007 — conf
Novel Programmable FIR Filter Based on Higher Radix Recoding for Low-Power and High-Performance Applications.
ICASSP (3)
Hsiao-Yun Chen, Shyh-Jye Jou
2006 J jnl
DC-Balance Low-Jitter Transmission Code for 4-PAM Signaling.
IEEE Trans. Circuits Syst. II Express Briefs
Hsiao-Yun Chen, Chih-Hsien Lin, Shyh-Jye Jou
2006 C conf
Memory reduction ICFO estimation architecture for DVB-T.
ISCAS
Ting-Zhen Wei, Shyh-Jye Jou, Muh-Tian Shiue
2006 J jnl
Parallel scrambler for high-speed applications.
IEEE Trans. Circuits Syst. II Express Briefs
Chih-Hsien Lin, Chih-Ning Chen, You-Jiun Wang, Ju-Yuan Hsiao, Shyh-Jye Jou
2005 — conf
A 12.5 Gbps CMOS input sampler for serial link receiver front end.
ISCAS (2)
Shyh-Jye Jou, Chih-Hsien Lin, Yen-I Wang
2005 J jnl
Multi-Gigabit Pre-Emphasis Design and Analysis for Serial Link.
IEICE Trans. Electron.
Chih-Hsien Lin, Chang-Hsiao Tsai, Chih-Ning Chen, Shyh-Jye Jou
2004 — conf
4/2 PAM serial link transmitter with tunable pre-emphasis.
ISCAS (1)
Chih-Hsien Lin, Chang-Hsiao Tsai, Chih-Ning Chen, Shyh-Jye Jou
2004 — conf
A design flow for multiplierless linear-phase FIR filters: from system specification to Verilog code.
ISCAS (5)
Kai-Yuan Jheng, Shyh-Jye Jou, An-Yeu Wu
2003 — conf
5Gbps serial link transmitter with pre-emphasis.
ASP-DAC
Chih-Hsien Lin, Chung-Hong Wang, Shyh-Jye Jou
2003 J jnl
Low-Power Embedded DSP Core for Communication Systems.
EURASIP J. Adv. Signal Process.
Ya-Lan Tsao, Wei-Hao Chen, Ming Hsuan Tan, Maw-Ching Lin, Shyh-Jye Jou
2003 — conf
Low-power digital CDMA receiver.
ASP-DAC
Ja-Sheng Liu, I-Hsin Chen, Yi-Chen Tsai, Shyh-Jye Jou
2003 — conf
Parameterized and low power DSP core for embedded systems.
ISCAS (5)
Ya-Lan Tsao, Ming Hsuan Tan, Jun-Xian Teng, Shyh-Jye Jou
2002 — conf
An embedded DSP core for wireless communication.
ISCAS (4)
Shyh-Jye Jou, Hsiao Ping Lee, Yi-Ting Chen, Ming Hsuan Tan, Ya-Lan Tsao
2002 — conf
Sub-word and reduced-width Booth multipliers for DSP applications.
ISCAS (3)
Meng-Hung Tsai, Yi-Ting Chen, Wen-Sheng Cheng, Jun-Xian Teng, Shyh-Jye Jou
2001 — conf
A serial link transceiver for USB2 high-speed mode.
ISCAS (4)
Shyh-Jye Jou, Shu-Hua Kuo, Jui-Ta Chiu, Chu King, Chien-Hsiung Lee, Tim Liu
2001 J jnl
Intrinsic response for analog module testing using an analog testability bus.
ACM Trans. Design Autom. Electr. Syst.
Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou
2001 J jnl
Low switching noise and load-adaptive output buffer design techniques.
IEEE J. Solid State Circuits
Shyh-Jye Jou, Shu-Hua Kuo, Jui-Ta Chiu, Tin-Hao Lin
2001 — conf
Low-power multiplierless FIR filter synthesizer based on CSD code.
ISCAS (4)
Maw-Ching Lin, Chien-Lung Chen, Ding-Yu Shin, Chin-Hung Lin, Shyh-Jye Jou
2000 C conf
Fixed-Width Multiplier for DSP Application.
ICCD
Shyh-Jye Jou, Hui-Hsuan Wang
1999 J jnl
Decentralized BIST Methodology for System Level Interconnects.
J. Electron. Test.
Chauchin Su, Shyh-Jye Jou
1998 — conf
An all digital phase-locked loop with modified binary search of frequency acquisition.
ICECS
Shyh-Jye Jou, Ya-Lan Tsao, I-Ying Yang
1998 — conf
Simultaneous switching noise analysis and low bouncing buffer design [CMOS ICs].
CICC
Shyh-Jye Jou, Wei-Chung Cheng, Yu-Tao Lin
1997 J jnl
A pipelined multiplier-accumulator using a high-speed, low-power static and dynamic full adder design.
IEEE J. Solid State Circuits
Shyh-Jye Jou, Chang-Yu Chen, En-Chung Yang, Chau-Chin Su
1997 A conf
Parasitic Effect Removal for Analog Measurement in P1149.4 Environment.
ITC
Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou
1997 — conf
Structural approach for performance driven ECC circuit synthesis.
ASP-DAC
Chauchin Su, Kathy Y. Chen, Shyh-Jye Jou
1996 — conf
Decentralized BIST for 1149.1 and 1149.5 Based Interconnects.
ED&TC
Chauchin Su, Shyh-Jye Jou, Yuan-Tzu Ting
1996 A conf
Metrology for analog module testing using analog testability bus.
ICCAD
Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou, Yuan-Tzu Ting
1996 — conf
Syndrome Simulation And Syndrome Test For Unscanned Interconnects.
Asian Test Symposium
Chauchin Su, Shyh-Shen Hwang, Shyh-Jye Jou, Yuan-Tzu Ting
1995 C conf
A Parallel Event-Driven MOS Timing Simulator on Distributed-Memory Multiprocessors.
ISCAS
Wen-Hsing Hsieh, Shyh-Jye Jou, Chauchin Su
1995 C conf
Circuits Design Optimization Using Symbolic Approach.
ISCAS
Shyh-Jye Jou, Kou-Fong Liu, Chauchin Su
1995 A conf
Impulse response fault model and fault extraction for functional level analog circuit diagnosis.
ICCAD
Chauchin Su, Shenshung Chiang, Shyh-Jye Jou
1994 A conf
An I
ITC
Chauchin Su, Kychin Hwang, Shyh-Jye Jou
1994 C conf
Hierarchical Techniques for Symbolic Analysis of Large Electronic Circuits.
ISCAS
Shyh-Jye Jou, Mei-Fang Perng, Chauchin Su, C. K. Wang
1994 — book
Mixed-mode simulation and analog multilevel simulation.
Resve A. Saleh, Shyh-Jye Jou, A. Richard Newton