Shyamapada Mukherjee

26 papers Journal 12Unranked 14
YearRankTypeTitle / Venue / Authors
2026 J jnl
A Novel Unified Approach to Deepfake Detection.
CoRR
Lord Sen, Shyamapada Mukherjee
2026 J jnl
Mapping Networks.
CoRR
Lord Sen, Shyamapada Mukherjee
2025 J jnl
QuIRK: Quantum-Inspired Re-uploading KAN.
CoRR
Vinayak Sharma, Ashish Padhy, Lord Sen, Vijay Jagdish Karanjkar, Sourav Behera, Shyamapada Mukherjee, Aviral Shrivastava
2025 J jnl
Symmetric Reduction Techniques for Quantum Graph Colouring.
CoRR
Lord Sen, Shyamapada Mukherjee
2024 — conf
A Novel Unified Approach to Deepfake Detection of Images.
ISED
Lord Sen, Shyamapada Mukherjee
2024 — conf
Energy and Delay Optimization for Task Offloading in IoT-Fog Environment with Homogeneous Logical Instances on Fog Devices.
ISED
Ritarani Sahu, Suchismita Chinara, Prabhanjan Mishra, Shyamapada Mukherjee
2024 — conf
Hybrid Classical-Quantum Neural Network for n-Dimensional Embedding.
ISED
Arnab Das, Shyamapada Mukherjee
2024 — conf
Quantum Circuit Optimization Techniques Using Iterative Pre-Conditioned Gradient Descent.
ISED
Suvankar Tudu, Shyamapada Mukherjee
2024 — conf
Testing the Effect of Hardware Trojans: A Case Study.
ISED
Sneh Agrawal, Shyamapada Mukherjee
2023 J jnl
An extract-then-abstract based method to generate disaster-news headlines using a DNN extractor followed by a transformer abstractor.
Inf. Process. Manag.
Sumanta Banerjee, Shyamapada Mukherjee, Sivaji Bandyopadhyay, Partha Pakray
2023 J jnl
PHetDP: A Placement Algorithm for Heterogeneous FPGAs with Delayed Packing.
Circuits Syst. Signal Process.
Sharbani Purkayastha, Shyamapada Mukherjee
2022 — conf
A Reward-based Framework for Recovery and Utilization of Recyclable Wastes using Blockchain.
OCIT
Yagnyasenee Sen Gupta, Shyamapada Mukherjee
2022 J jnl
Congestion-Aware Rectilinear Steiner Tree Construction Using PB-SAT.
J. Circuits Syst. Comput.
Sudeshna Kundu, Suchismita Roy, Shyamapada Mukherjee
2020 J jnl
Rectilinear Steiner Tree Construction Techniques Using PB-SAT-Based Methodology.
J. Circuits Syst. Comput.
Sudeshna Kundu, Suchismita Roy, Shyamapada Mukherjee
2019 J jnl
Architecture-aware routability-driven placer for large-scale mixed-size designs.
IET Circuits Devices Syst.
Prasun Datta, Shyamapada Mukherjee
2019 — conf
Gait Recognition using Segmented Motion Flow Energy Image.
ICCCNT
Shyamapada Mukherjee, Kunal Chaudhary, Priya Jain, Bishal Paul
2019 — conf
Spoken Language Recognition Using CNN.
ICIT
Shyamapada Mukherjee, Neeraj Shivam, Astha Gangwal, Lokesh Khaitan, Amlan Jyoti Das
2018 — conf
An Alternate Algorithmic Approach to FPGA Placement.
ICCCNT
Shyamapada Mukherjee, A. Nainwal, C. C. Das, Sharbani Purkayastha
2018 — conf
IPplacer: An Efficient 0-1 Integer Programming Based Placement for VLSI Circuits.
ICCCNT
Prasun Datta, Shyamapada Mukherjee
2017 — conf
K-nearest neighbour (KNN) approach using SAT based technique for rectilinear steiner tree construction.
ISED
Sudeshna Kundu, Suchismita Roy, Shyamapada Mukherjee
2017 — conf
Lookahead legalization based global placement for heterogeneous FPGAs.
ISED
Sharbani Purkayastha, Shyamapada Mukherjee
2017 J jnl
Via-Aware Dogleg Routing Using Boolean Satisfiability.
J. Circuits Syst. Comput.
Shyamapada Mukherjee, Suchismita Roy
2016 J jnl
Nearly-2-SAT Solutions for Segmented-Channel Routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shyamapada Mukherjee, Suchismita Roy
2015 — conf
Multi terminal net routing for island style FPGAs using nearly-2-SAT computation.
VDAT
Shyamapada Mukherjee, Suchismita Roy
2015 J jnl
SAT based solutions for detailed routing of island style FPGA architectures.
Microelectron. J.
Shyamapada Mukherjee, Suchismita Roy
2013 — conf
Congestion Balancing Global Router.
VDAT
Shyamapada Mukherjee, Jibesh Patra, Suchismita Roy