Shyam Akashe

30 papers Journal 15Unranked 15
YearRankTypeTitle / Venue / Authors
2026 J jnl
Investigating non-volatile memory architectures for neuromorphic systems with CMOS spike-timed synaptic plasticity.
Discov. Comput.
Joshika Sharma, Shyam Akashe, Govind Murari Upadhyay
2025 J jnl
Smart Street Light System Integrated with Internet-of-things based Sensors for Energy Monitoring.
Scalable Comput. Pract. Exp.
Sadhana Mishra, Bhupendra Dhakad, Shailendra Singh Ojha, Shyam Akashe
2024 — conf
Innovative Circuit Level Methodology for FinFET based Low-Power 6T SRAM Cell Design.
VDAT
Vishal Gupta, Sribhuvaneshwari H, Tanmaya Kumar Das, Saurabh Khandelwal, Shyam Akashe
2018 J jnl
Design and Enactment of Diverse Low Power Techniques Based Schmitt Trigger.
Wirel. Pers. Commun.
Mukesh Kumar Singh, Shyam Akashe
2018 J jnl
Holding State Performance Amelioration by Exploitation of NMOS Body Effect in 1T DRAM Cells.
Wirel. Pers. Commun.
Peter Bukelani Musiiwa, Shyam Akashe
2017 J jnl
Low Power Consuming 1 KB (32 × 32) Memory Array Using Compact 7T SRAM Cell.
Wirel. Pers. Commun.
Shalini Singh, Shyam Akashe
2016 — conf
A SDDG FinFET Based Op Amp with DSB Circuit.
ICTCS
Jainendra Tripathi, Ranjeet Singh Tomar, Shyam Akashe
2016 J jnl
An Innovative Design: MOS Based Full-Wave Centre-Tapped Rectifier.
Wirel. Pers. Commun.
Prateek Jain, Shyam Akashe
2016 — conf
Design and Analysis of New Efficient Multifin Low Leakage Switch Mode Power Supply.
ICTCS
Shubham Kumar, Prateek Jain, Shyam Akashe
2016 J jnl
Design of 8T Volatile and Non-Volatile RAM Cells with Improved Holding Phase Performance.
J. Low Power Electron.
Peter Bukelani Musiiwa, Shyam Akashe
2016 — conf
Design of Low Power Memristor Non-Volatile Dram Cell with Footer Switch.
ICTCS
Peter Bukelani Musiiwa, Shyam Akashe
2016 — conf
Design of low power 3-bit TIQ based ADC by using FinFET Technology.
ICTCS
Devansh Sinha, Shyam Akashe
2016 J jnl
FinFET Design Considerations Based on Schmitt Trigger with Slew Rate and Gain-Bandwidth Product Analysis.
Wirel. Pers. Commun.
Pawan Sharma, Saurabh Khandelwal, Shyam Akashe
2016 — conf
Novel Gating Technique in D-Latch for Low Power Application.
ICTCS
Akanksha Singh, Ayushi Marwah, Shyam Akashe
2016 — conf
Performance Augmentation of 2: 1 Mux Using Transmission Gate.
ICTCS
Mohit Vyas, Shyam Akashe
2016 — conf
Power and Area Efficient Capacitor Multiplier Technique for Multi-Fin Two Stage Opamp.
ICTCS
Aditya Raj, Shyam Akashe
2016 — conf
Power efficient optimal Operational Transconductance Amplifier Using Source Degeneration Technique.
ICTCS
Prateek Tiwari, Ranjeet Singh Tomar, Shyam Akashe
2016 — conf
Realization of Schmitt Trigger in Low Power SRAM Cell.
ICTCS
Nilotpal Arjun, Ayushi Marwah, Shyam Akashe
2015 J jnl
Enhanced Power Gating Schemes for Low Leakage Power and Low Ground Bounce Noise in Design of Ring Oscillator.
Wirel. Pers. Commun.
Sheetal Soni, Shyam Akashe
2015 J jnl
High performance 8 bit cascaded carry look ahead adder with precise power consumption.
Int. J. Commun. Syst.
Raj Johri, Shyam Akashe, Sanjay Sharma
2015 J jnl
Modeling and Optimization of Nano-Scale Sensing Shorted Gate FinFET D Flip-Flop Using AVL.
J. Low Power Electron.
Pooja Joshi, Saurabh Khandelwal, Shyam Akashe
2014 J jnl
Analyzing the Impact of Bootstrapped ADC with Augmented NMOS Sleep Transistors Configuration on Performance Parameters.
Circuits Syst. Signal Process.
Prateek Jain, Shyam Akashe
2014 J jnl
Estimation of high performance in Schmitt triggers with stacking power-gating techniques in 45 nm CMOS technology.
Int. J. Commun. Syst.
Anshul Saxena, Akansha Shrivastava, Shyam Akashe
2014 J jnl
Modeling and Analysis of Low Power 10 T Full Adder with Reduced Ground Bounce noise.
J. Circuits Syst. Comput.
Raghvendra Singh, Shyam Akashe
2013 J jnl
Leakage Current Reduction Techniques for 7T SRAM Cell in 45 nm Technology.
Wirel. Pers. Commun.
Shyam Akashe, Sanjay Sharma
2012 — conf
Analysis and Simulation of Full Adder Design Using MTCMOS Technique.
BIC-TA (2)
Richa Saraswat, Shyam Akashe, Shyam Babu
2012 — conf
Analyzing and Minimization Effect of Temperature Variation of 2: 1 MUX Using FINFET.
BIC-TA (2)
Khushboo Mishra, Shyam Akashe, Satish Kumar
2012 — conf
Effect of MT and VT CMOS, on Transmission Gate Logic for Low Power 4: 1 MUX in 45 nm Technology.
BIC-TA (2)
Meenakshi Mishra, Shyam Akashe, Shyam Babu
2012 — conf
Implementation of 2: 4 DECODER for low leakage Using MTCMOS Technique in 45 Nanometre Regime.
BIC-TA (2)
Shyam Akashe, Rajeev Sharma, Nitesh Tiwari, Jayram Shrivas
2012 — conf
Modeling and Simulation of High Speed 8T SRAM Cell.
BIC-TA (2)
Raj Johri, Ravindra Singh Kushwah, Raghvendra Singh, Shyam Akashe