Shuyao Cheng - RankMe

19 papers A* 5Journal 13Unranked 1

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	AGON: Automated Design Framework for Customizing Processors From ISA Documents. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chongxiao Li, Di Huang, Pengwei Jin, TianYun Ma, Husheng Han, Shuyao Cheng, Yifan Hao, Yongwei Zhao, Guanglin Xu, Zidong Du, Rui Zhang, Xiaqing Li, Yuanbo Wen, Xing Hu, Qi Guo
2026	J	`jnl`	LocalV: Exploiting Information Locality for IP-level Verilog Generation. CoRR Han-Qi Lyu, Di Huang, Yaoyu Zhu, Kangcheng Liu, Bohan Dou, Chongxiao Li, Pengwei Jin, Shuyao Cheng, Rui Zhang, Zidong Du, Qi Guo, Xing Hu, Yunji Chen
2026	A*	`conf`	QiMeng-CRUX: Narrowing the Gap Between Natural Language and Verilog via Core Refined Understanding eXpression. AAAI Lei Huang, Rui Zhang, Jiaming Guo, Yang Zhang, Di Huang, Shuyao Cheng, Pengwei Jin, Chongxiao Li, Zidong Du, Xing Hu, Yunji Chen, Qi Guo
2025	—	`conf`	Area-Efficient Automated Logic Design with Monte-Carlo Tree Search. APPT Shuyao Cheng, Xiangtao Guan, Zidong Du
2025	A*	`conf`	Automated Superscalar Processor Design by Learning Data Dependencies. IJCAI Shuyao Cheng, Rui Zhang, Wenkai He, Pengwei Jin, Chongxiao Li, Zidong Du, Xing Hu, Yifan Hao, Guanglin Xu, Yuanbo Wen, Ling Li, Qi Guo, Yunji Chen
2025	J	`jnl`	CodeV-R1: Reasoning-Enhanced Verilog Generation. CoRR Yaoyu Zhu, Di Huang, Han-Qi Lyu, Xiaoyun Zhang, Chongxiao Li, Wenxuan Shi, Yutong Wu, Jianan Mu, Jinghua Wang, Yang Zhao, Pengwei Jin, Shuyao Cheng, Shengwen Liang, Xishan Zhang, Rui Zhang, Zidong Du, Qi Guo, Xing Hu, Yunji Chen
2025	J	`jnl`	QiMeng-CPU-v2: Automated Superscalar Processor Design by Learning Data Dependencies. CoRR Shuyao Cheng, Rui Zhang, Wenkai He, Pengwei Jin, Chongxiao Li, Zidong Du, Xing Hu, Yifan Hao, Guanglin Xu, Yuanbo Wen, Ling Li, Qi Guo, Yunji Chen
2025	J	`jnl`	QiMeng-CRUX: Narrowing the Gap between Natural Language and Verilog via Core Refined Understanding eXpression. CoRR Lei Huang, Rui Zhang, Jiaming Guo, Yang Zhang, Di Huang, Shuyao Cheng, Pengwei Jin, Chongxiao Li, Zidong Du, Xing Hu, Qi Guo, Yunji Chen
2025	J	`jnl`	QiMeng-SALV: Signal-Aware Learning for Verilog Code Generation. CoRR Yang Zhang, Rui Zhang, Jiaming Guo, Lei Huang, Di Huang, Yunpu Zhao, Shuyao Cheng, Pengwei Jin, Chongxiao Li, Zidong Du, Xing Hu, Qi Guo, Yunji Chen
2025	J	`jnl`	QiMeng: Fully Automated Hardware and Software Design for Processor Chip. CoRR Rui Zhang, Yuanbo Wen, Shuyao Cheng, Di Huang, Shaohui Peng, Jiaming Guo, Pengwei Jin, Jiacheng Zhao, Tianrui Ma, Yaoyu Zhu, Yifan Hao, Yongwei Zhao, Shengwen Liang, Ying Wang, Xing Hu, Zidong Du, Huimin Cui, Ling Li, Qi Guo, Yunji Chen
2025	J	`jnl`	RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs. CoRR Pengwei Jin, Di Huang, Chongxiao Li, Shuyao Cheng, Yang Zhao, Xinyao Zheng, Jiaguo Zhu, Shuyi Xing, Bohan Dou, Rui Zhang, Zidong Du, Qi Guo, Xing Hu
2024	J	`jnl`	AGON: Automated Design Framework for Customizing Processors from ISA Documents. CoRR Chongxiao Li, Di Huang, Pengwei Jin, TianYun Ma, Husheng Han, Shuyao Cheng, Yifan Hao, Yongwei Zhao, Guanglin Xu, Zidong Du, Rui Zhang, Xiaqing Li, Yuanbo Wen, Yanjun Wu, Chen Zhao, Xing Hu, Qi Guo
2024	A*	`conf`	Automated CPU Design by Learning from Input-Output Examples. IJCAI Shuyao Cheng, Pengwei Jin, Qi Guo, Zidong Du, Rui Zhang, Xing Hu, Yongwei Zhao, Yifan Hao, Xiangtao Guan, Husheng Han, Zhengyue Zhao, Ximing Liu, Xishan Zhang, Yuejie Chu, Weilong Mao, Tianshi Chen, Yunji Chen
2024	A*	`conf`	Revisiting Automatic Pipelining: Gate-level Forwarding and Speculation. DAC Shuyao Cheng, Chongxiao Li, Zidong Du, Rui Zhang, Xing Hu, Xiaqing Li, Guanglin Xu, Yuanbo Wen, Qi Guo
2023	J	`jnl`	Pushing the Limits of Machine Design: Automated CPU Design with AI. CoRR Shuyao Cheng, Pengwei Jin, Qi Guo, Zidong Du, Rui Zhang, Yunhao Tian, Xing Hu, Yongwei Zhao, Yifan Hao, Xiangtao Guan, Husheng Han, Zhengyue Zhao, Ximing Liu, Ling Li, Xishan Zhang, Yuejie Chu, Weilong Mao, Tianshi Chen, Yunji Chen
2022	A*	`conf`	Cambricon-P: A Bitflow Architecture for Arbitrary Precision Computing. MICRO Yifan Hao, Yongwei Zhao, Chenxiao Liu, Zidong Du, Shuyao Cheng, Xiaqing Li, Xing Hu, Qi Guo, Zhiwei Xu, Tianshi Chen
2019	J	`jnl`	BSHIFT: A Low Cost Deep Neural Networks Accelerator. Int. J. Parallel Program. Yong Yu, Tian Zhi, Xuda Zhou, Shaoli Liu, Yunji Chen, Shuyao Cheng
2018	J	`jnl`	Decentralized Fault Tolerant Control for a Class of Interconnected Nonlinear Systems. IEEE Trans. Cybern. Shuai Shao, Hao Yang, Bin Jiang, Shuyao Cheng
2016	J	`jnl`	An integrated fault estimation and accommodation design for a class of complex networks. Neurocomputing Shuyao Cheng, Hao Yang, Bin Jiang