Shusuke Yoshimoto

45 papers A 1C 4Journal 19Unranked 21

Year	Rank	Type	Title / Venue / Authors
2024	—	`conf`	Estimation of the Stages of Labor Using a Multichannel Electrohysterogram Sensor and Conditional Variational Autoencoder. EMBC Minon Kushihashi, Shintaro Izumi, Hirokazu Iida, Shusuke Yoshimoto, Tsuyoshi Takiuchi, Kazuya Mimura, Takeshi Kanagawa, Aiko Kakigano, Tsuyoshi Sekitani, Masayuki Endoh, Tadashi Kimura, Hiroshi Kawaguchi
2022	J	`jnl`	HARU Sleep: A Deep Learning-Based Sleep Scoring System With Wearable Sheet-Type Frontal EEG Sensors. IEEE Access Shoya Matsumori, Kosei Teramoto, Hiroya Iyori, Takanori Soda, Shusuke Yoshimoto, Haruo Mizutani
2020	J	`jnl`	Printable Transparent Microelectrodes toward Mechanically and Visually Imperceptible Electronics. Adv. Intell. Syst. Ashuya Takemoto, Teppei Araki, Takafumi Uemura, Yuki Noda, Shusuke Yoshimoto, Shintaro Izumi, Shuichi Tsuruta, Tsuyoshi Sekitani
2020	J	`jnl`	Printable Transparent Microelectrodes toward Mechanically and Visually Imperceptible Electronics. Adv. Intell. Syst. Ashuya Takemoto, Teppei Araki, Takafumi Uemura, Yuki Noda, Shusuke Yoshimoto, Shintaro Izumi, Shuichi Tsuruta, Tsuyoshi Sekitani
2019	J	`jnl`	A 28-nm FD-SOI 8T Dual-Port SRAM for Low-Energy Image Processor With Selective Sourceline Drive Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. Haruki Mori, Tomoki Nakagawa, Yuki Kitahara, Yuta Kawamoto, Kenta Takagi, Shusuke Yoshimoto, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2019	—	`conf`	Noise Evaluation System for Biosignal Sensors Using Pseudo-Skin and Helmholtz Coil. ISMICT Misaki Inaoka, Shintaro Izumi, Shusuke Yoshimoto, Toshikazu Nezu, Yuki Noda, Teppei Araki, Takafumi Uemura, Tsuyoshi Sekitani
2017	—	`conf`	A patch-type wireless forehead pulse oximeter for SpO2 measurement. BioCAS Afreen Azhari, Shusuke Yoshimoto, Toshikazu Nezu, Hirokazu Iida, Hiroki Ota, Yuki Noda, Teppei Araki, Takafumi Uemura, Tsuyoshi Sekitani, Katsuyuki Morii
2017	J	`jnl`	Flexible electronics for bio-signal monitoring in implantable applications. IEICE Electron. Express Shusuke Yoshimoto, Teppei Araki, Takafumi Uemura, Yuki Noda, Tsuyoshi Sekitani
2017	—	`conf`	Flexible organic TFT bio-signal amplifier using reliable chip component assembly process with conductive adhesive. EMBC Shusuke Yoshimoto, Takafumi Uemura, Mihoko Akiyama, Yoshihiro Ihara, Satoshi Otake, Tomoharu Fujii, Teppei Araki, Tsuyoshi Sekitani
2017	—	`conf`	Flexible sensor sheet for real-time pressure monitoring in artificial knee joint during total knee arthroplasty. EMBC Fumika Tanabe, Shusuke Yoshimoto, Yuki Noda, Teppei Araki, Takafumi Uemura, Yoshinori Takeuchi, Masaharu Imai, Tsuyoshi Sekitani
2017	—	`conf`	Wearable pulse wave velocity sensor using flexible piezoelectric film array. BioCAS Takumi Katsuura, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Shusuke Yoshimoto, Tsuyoshi Sekitani
2016	J	`jnl`	A 28-nm 484-fJ/writecycle 650-fJ/readcycle 8T Three-Port FD-SOI SRAM for Image Processor. IEICE Trans. Electron. Haruki Mori, Yohei Umeki, Shusuke Yoshimoto, Shintaro Izumi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
2016	J	`jnl`	A Counter-based Read Circuit Tolerant to Process Variation for 0.4-V Operating STT-MRAM. IPSJ Trans. Syst. LSI Des. Methodol. Yohei Umeki, Koji Yanagida, Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Koji Tsunoda, Toshihiro Sugii
2016	—	`conf`	An low-energy 8T dual-port SRAM for image processor with selective sourceline drive scheme in 28-nm FD-SOI process technology. ICECS Haruki Mori, Tomoki Nakagawa, Yuki Kitahara, Yuta Kawamoto, Kenta Takagi, Shusuke Yoshimoto, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2016	—	`conf`	Implantable wireless 64-channel system with flexible ECoG electrode and optogenetics probe. BioCAS Shusuke Yoshimoto, Teppei Araki, Takafumi Uemura, Toshikazu Nezu, Tsuyoshi Sekitani, Takafumi Suzuki, Fumiaki Yoshida, Masayuki Hirata
2016	—	`conf`	Wireless EEG patch sensor on forehead using on-demand stretchable electrode sheet and electrode-tissue impedance scanner. EMBC Shusuke Yoshimoto, Teppei Araki, Takafumi Uemura, Toshikazu Nezu, Masaya Kondo, Kenichi Sasai, Masayuki Iwase, Hideki Satake, Akio Yoshida, Mitsuru Kikuchi, Tsuyoshi Sekitani
2015	—	`conf`	A 298-fJ/writecycle 650-fJ/readcycle 8T three-port SRAM in 28-nm FD-SOI process technology for image processor. CICC Haruki Mori, Tomoki Nakagawa, Yuki Kitahara, Yuta Kawamoto, Kenta Takagi, Shusuke Yoshimoto, Shintaro Izumi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
2015	C	`conf`	A low power 6T-4C non-volatile memory using charge sharing and non-precharge techniques. ISCAS Tomoki Nakagawa, Shintaro Izumi, Koji Yanagida, Yuki Kitahara, Shusuke Yoshimoto, Yohei Umeki, Haruki Mori, Hiroto Kitahara, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Masahiko Yoshimoto
2015	—	`conf`	A negative-resistance sense amplifier for low-voltage operating STT-MRAM. ASP-DAC Yohei Umeki, Koji Yanagida, Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Koji Tsunoda, Toshihiro Sugii
2015	J	`jnl`	Normally Off ECG SoC With Non-Volatile MCU and Noise Tolerant Heartbeat Detector. IEEE Trans. Biomed. Circuits Syst. Shintaro Izumi, Ken Yamashita, Masanao Nakano, Shusuke Yoshimoto, Tomoki Nakagawa, Yozaburo Nakai, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Hiroshi Nakajima, Toshikazu Shiga, Masahiko Yoshimoto
2014	—	`conf`	A 6.14µA normally-off ECG-SoC with noise tolerant heart rate extractor for wearable healthcare systems. BioCAS Shintaro Izumi, Ken Yamashita, Masanao Nakano, Tomoki Nakagawa, Yuki Kitahara, Koji Yanagida, Shusuke Yoshimoto, Hiroshi Kawaguchi, Hiromitsu Kimura, Kyoji Marumoto, Takaaki Fuchikami, Yoshikazu Fujimori, Hiroshi Nakajima, Toshikazu Shiga, Masahiko Yoshimoto
2014	C	`conf`	A 6T-4C shadow memory using plate line and word line boosting. ISCAS Tomoki Nakagawa, Shintaro Izumi, Shusuke Yoshimoto, Koji Yanagida, Yuki Kitahara, Hiroshi Kawaguchi, Masahiko Yoshimoto
2014	J	`jnl`	STT-MRAM Operating at 0.38V Using Negative-Resistance Sense Amplifier. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yohei Umeki, Koji Yanagida, Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Koji Tsunoda, Toshihiro Sugii
2014	J	`jnl`	Soft-Error Resilient and Margin-Enhanced N-P Reversed 6T SRAM Bitcell. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto
2013	—	`conf`	A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM using low-power disturb mitigation technique. ASP-DAC Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto
2013	—	`conf`	A 40-nm 8T SRAM with selective source line control of read bitlines and address preset structure. CICC Shusuke Yoshimoto, Shinji Miyano, Makoto Takamiya, Hirofumi Shinohara, Hiroshi Kawaguchi, Masahiko Yoshimoto
2013	—	`conf`	A physical unclonable function chip exploiting load transistors' variation in SRAM bitcells. ASP-DAC Shunsuke Okumura, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto
2013	J	`jnl`	Multiple-Cell-Upset Tolerant 6T SRAM Using NMOS-Centered Cell Layout. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shusuke Yoshimoto, Shunsuke Okumura, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
2012	J	`jnl`	A 0.15-µm FD-SOI Substrate Bias Control SRAM with Inter-Die Variability Compensation Scheme. IEICE Trans. Electron. Shunsuke Okumura, Hidehiro Fujiwara, Kosuke Yamaguchi, Shusuke Yoshimoto, Masahiko Yoshimoto, Hiroshi Kawaguchi
2012	J	`jnl`	A 128-bit Chip Identification Generating Scheme Exploiting Load Transistors' Variation in SRAM Bitcells. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shunsuke Okumura, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto
2012	J	`jnl`	A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme. IEICE Trans. Electron. Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto
2012	—	`conf`	A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction. ISQED Masaharu Terada, Shusuke Yoshimoto, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto
2012	J	`jnl`	A 40-nm 256-Kb Half-Select Resilient 8T SRAM with Sequential Writing Technique. IEICE Electron. Express Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto
2012	A	`conf`	A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme. ISLPED Shusuke Yoshimoto, Masaharu Terada, Youhei Umeki, Shunsuke Okumura, Atsushi Kawasumi, Toshikazu Suzuki, Shinichi Moriwaki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto
2012	—	`conf`	Bit error rate estimation in SRAM considering temperature fluctuation. ISQED Yuki Kagiyama, Shunsuke Okumura, Koji Yanagida, Shusuke Yoshimoto, Yohei Nakata, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2012	J	`jnl`	Bit-Error and Soft-Error Resilient 7T/14T SRAM with 150-nm FD-SOI Process. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shusuke Yoshimoto, Takuro Amashita, Shunsuke Okumura, Koji Nii, Masahiko Yoshimoto, Hiroshi Kawaguchi
2012	J	`jnl`	Low-energy block-level instantaneous comparison 7T SRAM for dual modular redundancy. IEICE Electron. Express Shunsuke Okumura, Yohei Nakata, Koji Yanagida, Yuki Kagiyama, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto
2012	J	`jnl`	Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure. IEICE Trans. Electron. Shusuke Yoshimoto, Takuro Amashita, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto
2012	C	`conf`	Neutron-induced soft error rate estimation for SRAM using PHITS. IOLTS Shusuke Yoshimoto, Takuro Amashita, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2011	J	`jnl`	7T SRAM Enabling Low-Energy Instantaneous Block Copy and Its Application to Transactional Memory. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shunsuke Okumura, Yuki Kagiyama, Yohei Nakata, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto
2011	—	`conf`	A 128-bit chip identification generating scheme exploiting SRAM bitcells with failure rate of 4.45 × 10 ESSCIRC Shunsuke Okumura, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto
2011	—	`conf`	Low-power block-level instantaneous comparison 7T SRAM for dual modular redundancy. CICC Shunsuke Okumura, Yohei Nakata, Koji Yanagida, Yuki Kagiyama, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto
2011	C	`conf`	Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure. IOLTS Shusuke Yoshimoto, Takuro Amashita, D. Kozuwa, Taiga Takata, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Hiroshi Kawaguchi, Masahiko Yoshimoto
2010	—	`conf`	7T SRAM enabling low-energy simultaneous block copy. CICC Shunsuke Okumura, Shusuke Yoshimoto, Kosuke Yamaguchi, Yohei Nakata, Hiroshi Kawaguchi, Masahiko Yoshimoto
2009	—	`conf`	A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme. ISQED Shunsuke Okumura, Yusuke Iguchi, Shusuke Yoshimoto, Hidehiro Fujiwara, Hiroki Noguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto