Shuso Fujii

14 papers A 1Journal 9Unranked 4
YearRankTypeTitle / Venue / Authors
2012 J jnl
An Embedded DRAM Technology for High-Performance NAND Flash Memories.
IEEE J. Solid State Circuits
Daisaburo Takashima, Mitsuhiro Noguchi, Noboru Shibata, Kazushige Kanda, Hiroshi Sukegawa, Shuso Fujii
2011 J jnl
A 128 Mb Chain FeRAM and System Design for HDD Application and Enhanced HDD Performance.
IEEE J. Solid State Circuits
Daisaburo Takashima, Yasushi Nagadomi, Kosuke Hatsuda, Yohji Watanabe, Shuso Fujii
2011 J jnl
A Scalable Shield-Bitline-Overdrive Technique for Sub-1.5 V Chain FeRAMs.
IEEE J. Solid State Circuits
Daisaburo Takashima, Hidehiro Shiga, Daisuke Hashimoto, Tadashi Miyakawa, Shinichiro Shiratake, Katsuhiko Hoya, Ryu Ogiwara, Ryosuke Takizawa, Ryosuke Doumae, Ryo Fukuda, Yohji Watanabe, Shuso Fujii, Tohru Ozaki, Hiroyuki Kanaya, Susumu Shuto, Koji Yamakawa, Iwao Kunishima, Takeshi Hamamoto, Akihiro Nitayama
2011 — conf
An embedded DRAM technology for high-performance NAND flash memories.
ISSCC
Daisaburo Takashima, Mitsuhiro Noguchi, Noboru Shibata, Kazushige Kanda, Hiroshi Sukegawa, Shuso Fujii
2010 J jnl
A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes.
IEEE J. Solid State Circuits
Hidehiro Shiga, Daisaburo Takashima, Shinichiro Shiratake, Katsuhiko Hoya, Tadashi Miyakawa, Ryu Ogiwara, Ryo Fukuda, Ryosuke Takizawa, Kosuke Hatsuda, Fumiyoshi Matsuoka, Yasushi Nagadomi, Daisuke Hashimoto, Hisaaki Nishimura, Takeshi Hioka, Sumiko M. Doumae, Shoichi Shimizu, Mitsumo Kawano, Toyoki Taguchi, Yohji Watanabe, Shuso Fujii, Tohru Ozaki, Hiroyuki Kanaya, Yoshinori Kumura, Yoshiro Shimojo, Yuki Yamada, Yoshihiro Minami, Susumu Shuto, Koji Yamakawa, Soichi Yamazaki, Iwao Kunishima, Takeshi Hamamoto, Akihiro Nitayama, Tohru Furuyama
2010 J jnl
A 64-Mb Chain FeRAM With Quad BL Architecture and 200 MB/s Burst Mode.
IEEE Trans. Very Large Scale Integr. Syst.
Katsuhiko Hoya, Daisaburo Takashima, Shinichiro Shiratake, Ryu Ogiwara, Tadashi Miyakawa, Hidehiro Shiga, Sumiko M. Doumae, Sumito Ohtsuki, Yoshinori Kumura, Susumu Shuto, Tohru Ozaki, Koji Yamakawa, Iwao Kunishima, Akihiro Nitayama, Shuso Fujii
2010 — conf
A scalable shield-bitline-overdrive technique for 1.3V Chain FeRAM.
ISSCC
Daisaburo Takashima, Hidehiro Shiga, Daisuke Hashimoto, Tadashi Miyakawa, Shinichiro Shiratake, Katsuhiko Hoya, Ryu Ogiwara, Ryosuke Takizawa, Ryosuke Doumae, Ryo Fukuda, Yohji Watanabe, Shuso Fujii, Tohru Ozaki, Hiroyuki Kanaya, Susumu Shuto, Koji Yamakawa, Iwao Kunishima, Takeshi Hamamoto, Akihiro Nitayama
2009 — conf
A 1.6GB/s DDR2 128Mb chain FeRAM with scalable octal bitline and sensing schemes.
ISSCC
Hidehiro Shiga, Daisaburo Takashima, Shinichiro Shiratake, Katsuhiko Hoya, Tadashi Miyakawa, Ryu Ogiwara, Ryo Fukuda, Ryosuke Takizawa, Kosuke Hatsuda, Fumiyoshi Matsuoka, Yasushi Nagadomi, Daisuke Hashimoto, Hisaaki Nishimura, Takeshi Hioka, Sumiko M. Doumae, Shoichi Shimizu, Mitsumo Kawano, Toyoki Taguchi, Yohji Watanabe, Shuso Fujii, Tohru Ozaki, Hiroyuki Kanaya, Yoshinori Kumura, Yoshiro Shimojo, Yuki Yamada, Yoshihiro Minami, Susumu Shuto, Koji Yamakawa, Soichi Yamazaki, Iwao Kunishima, Takeshi Hamamoto, Akihiro Nitayama, Tohru Furuyama
2006 — conf
A 64Mb Chain FeRAM with Quad-BL Architecture and 200MB/s Burst Mode.
ISSCC
Katsuhiko Hoya, Daisaburo Takashima, Shinichiro Shiratake, Ryu Ogiwara, Tadashi Miyakawa, Hidehiro Shiga, Sumiko M. Doumae, Sumito Ohtsuki, Yoshinori Kumura, Susumu Shuto, Tohru Ozaki, Koji Yamakawa, Iwao Kunishima, Akihiro Nitayama, Shuso Fujii
2006 J jnl
Design of a 128-mb SOI DRAM using the floating body cell (FBC).
IEEE J. Solid State Circuits
Takashi Ohsawa, Katsuyuki Fujita, Kosuke Hatsuda, Tomoki Higashi, Tomoaki Shino, Yoshihiro Minami, Hiroomi Nakajima, Mutsuo Morikado, Kazumi Inoh, Takeshi Hamamoto, Shigeyoshi Watanabe, Shuso Fujii, Tohru Furuyama
2004 A conf
Post-Packaging Auto Repair Techniques for Fast Row Cycle Embedded DRAM.
ITC
Osamu Wada, Toshimasa Namekawa, Hiroshi Ito, Atsushi Nakayama, Shuso Fujii
1997 J jnl
Flexible test mode approach for 256-Mb DRAM.
IEEE J. Solid State Circuits
Toshiaki Kirihata, Hing Wong, John K. DeBrosse, Yohji Watanabe, Takahiko Hara, Munehiro Yoshida, Matthew R. Wordeman, Shuso Fujii, Yoshiaki Asao, Bo Krsnik
1996 J jnl
A 286 mm
IEEE J. Solid State Circuits
Yohji Watanabe, Ring Wong, Toshiaki Kirihata, Daisuke Kato, John K. DeBrosse, Takahiko Rara, Munehiro Yoshida, Rideo Mukai, Khandker N. Quader, Takeshi Nagai, Peter Poechmueller, Peter Pfefferl, Matthew R. Wordeman, Shuso Fujii
1996 J jnl
Fault-tolerant designs for 256 Mb DRAM.
IEEE J. Solid State Circuits
Toshiaki Kirihata, Yohji Watanabe, Hing Wong, John K. DeBrosse, Munehiro Yoshida, Daisuke Kato, Shuso Fujii, Matthew R. Wordeman, Peter Poechmueller, Stephen A. Parke, Yoshiaki Asao