Shuo Wang - RankMe

19 papers A* 6A 3B 1Journal 5Unranked 4

Year	Rank	Type	Title / Venue / Authors
2021	A*	`conf`	PipeZK: Accelerating Zero-Knowledge Proof with a Pipelined Architecture. ISCA Ye Zhang, Shuo Wang, Xian Zhang, Jiangbin Dong, Xingzhong Mao, Fan Long, Cong Wang, Dong Zhou, Mingyu Gao, Guangyu Sun
2020	A*	`conf`	FlexTensor: An Automatic Schedule Exploration and Optimization Framework for Tensor Computation on Heterogeneous System. ASPLOS Size Zheng, Yun Liang, Shuo Wang, Renze Chen, Kaiwen Sheng
2019	A*	`conf`	E-LSTM: Efficient Inference of Sparse LSTM on Embedded Heterogeneous System. DAC Runbin Shi, Junjie Liu, Hayden Kwok-Hay So, Shuo Wang, Yun Liang
2019	A*	`conf`	Poly: Efficient Heterogeneous System and Application Management for Interactive Applications. HPCA Shuo Wang, Yun Liang, Wei Zhang
2019	A	`conf`	REQ-YOLO: A Resource-Aware, Efficient Quantization Framework for Object Detection on FPGAs. FPGA Caiwen Ding, Shuo Wang, Ning Liu, Kaidi Xu, Yanzhi Wang, Yun Liang
2019	J	`jnl`	REQ-YOLO: A Resource-Aware, Efficient Quantization Framework for Object Detection on FPGAs. CoRR Caiwen Ding, Shuo Wang, Ning Liu, Kaidi Xu, Yanzhi Wang, Yun Liang
2018	—	`conf`	Analytical Two-Level Near Threshold Cache Exploration for Low Power Biomedical Applications. ACA Yun Liang, Shuo Wang, Tulika Mitra, Yajun Ha
2018	A	`conf`	C-LSTM: Enabling Efficient LSTM using Structured Compression Techniques on FPGAs. FPGA Shuo Wang, Zhe Li, Caiwen Ding, Bo Yuan, Qinru Qiu, Yanzhi Wang, Yun Liang
2018	J	`jnl`	C-LSTM: Enabling Efficient LSTM using Structured Compression Techniques on FPGAs. CoRR Shuo Wang, Zhe Li, Caiwen Ding, Bo Yuan, Yanzhi Wang, Qinru Qiu, Yun Liang
2018	—	`conf`	Efficient Recurrent Neural Networks using Structured Matrices in FPGAs. ICLR (Workshop) Zhe Li, Shuo Wang, Caiwen Ding, Qinru Qiu, Yanzhi Wang, Yun Liang
2018	J	`jnl`	Efficient Recurrent Neural Networks using Structured Matrices in FPGAs. CoRR Zhe Li, Shuo Wang, Caiwen Ding, Qinru Qiu, Yanzhi Wang, Yun Liang
2018	J	`jnl`	FlexCL: A Model of Performance and Power for OpenCL Workloads on FPGAs. IEEE Trans. Computers Yun Liang, Shuo Wang, Wei Zhang
2017	A*	`conf`	A Comprehensive Framework for Synthesizing Stencil Algorithms on FPGAs using OpenCL Model. DAC Shuo Wang, Yun Liang
2017	A	`conf`	A Framework for Iterative Stencil Algorithm Synthesis on FPGAs from OpenCL Programming Model (Abstract Only). FPGA Shuo Wang, Yun Liang
2017	A*	`conf`	FlexCL: An Analytical Performance Model for OpenCL Workloads on Flexible FPGAs. DAC Shuo Wang, Yun Liang, Wei Zhang
2016	J	`jnl`	Performance-Centric Optimization for Racetrack Memory Based Register File on GPUs. J. Comput. Sci. Technol. Yun Liang, Shuo Wang
2016	—	`conf`	Performance-centric register file design for GPUs using racetrack memory. ASP-DAC Shuo Wang, Yun Liang, Chao Zhang, Xiaolong Xie, Guangyu Sun, Yongpan Liu, Yu Wang, Xiuhong Li
2015	B	`conf`	Hierarchical Deployment and Control of Energy Storage Devices in Data Centers. CLOUD Shuo Wang, Yanzhi Wang, Xue Lin, Massoud Pedram
2015	—	`conf`	Quantitative performance and power analysis of LTE using high level synthesis. ASICON Yun Liang, Shuo Wang