Shunsuke Okumura

38 papers A 2Misc 1Journal 18Unranked 17
YearRankTypeTitle / Venue / Authors
2024 — conf
20.3 A 23.9TOPS/W @ 0.8V, 130TOPS AI Accelerator with 16× Performance-Accelerable Pruning in 14nm Heterogeneous Embedded MPU for Real-Time Robot Applications.
ISSCC
Koichi Nose, Taro Fujii, Katsumi Togawa, Shunsuke Okumura, Kentaro Mikami, Daichi Hayashi, Teruhito Tanaka, Takao Toi
2019 — conf
A Ternary Based Bit Scalable, 8.80 TOPS/W CNN accelerator with Many-core Processing-in-memory Architecture with 896K synapses/mm
VLSI Circuits
Shunsuke Okumura, Makoto Yabuuchi, Kenichiro Hijioka, Koichi Nose
2014 J jnl
A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation.
IEICE Trans. Electron.
Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata, Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai, Hiroshi Kawaguchi, Masahiko Yoshimoto
2014 — conf
A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement.
ISQED
Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata, Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai, Hiroshi Kawaguchi, Masahiko Yoshimoto
2013 — conf
A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM using low-power disturb mitigation technique.
ASP-DAC
Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto
2013 — conf
A physical unclonable function chip exploiting load transistors' variation in SRAM bitcells.
ASP-DAC
Shunsuke Okumura, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto
2013 J jnl
Multiple-Cell-Upset Tolerant 6T SRAM Using NMOS-Centered Cell Layout.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Shusuke Yoshimoto, Shunsuke Okumura, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
2013 J jnl
Reconfiguring Cache Associativity: Adaptive Cache Design for Wide-Range Reliable Low-Voltage Operation Using 7T/14T SRAM.
IEICE Trans. Electron.
Jinwook Jung, Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto
2012 J jnl
0.5-V 4-MB Variation-Aware Cache Architecture Using 7T/14T SRAM and Its Testing Scheme.
Inf. Media Technol.
Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto
2012 J jnl
0.5-V 4-MB Variation-Aware Cache Architecture Using 7T/14T SRAM and Its Testing Scheme.
IPSJ Trans. Syst. LSI Des. Methodol.
Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto
2012 J jnl
A 0.15-µm FD-SOI Substrate Bias Control SRAM with Inter-Die Variability Compensation Scheme.
IEICE Trans. Electron.
Shunsuke Okumura, Hidehiro Fujiwara, Kosuke Yamaguchi, Shusuke Yoshimoto, Masahiko Yoshimoto, Hiroshi Kawaguchi
2012 J jnl
A 128-bit Chip Identification Generating Scheme Exploiting Load Transistors' Variation in SRAM Bitcells.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Shunsuke Okumura, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto
2012 J jnl
A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme.
IEICE Trans. Electron.
Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto
2012 — conf
A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction.
ISQED
Masaharu Terada, Shusuke Yoshimoto, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto
2012 J jnl
A 40-nm 256-Kb Half-Select Resilient 8T SRAM with Sequential Writing Technique.
IEICE Electron. Express
Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto
2012 A conf
A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme.
ISLPED
Shusuke Yoshimoto, Masaharu Terada, Youhei Umeki, Shunsuke Okumura, Atsushi Kawasumi, Toshikazu Suzuki, Shinichi Moriwaki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto
2012 — conf
Bit error rate estimation in SRAM considering temperature fluctuation.
ISQED
Yuki Kagiyama, Shunsuke Okumura, Koji Yanagida, Shusuke Yoshimoto, Yohei Nakata, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2012 J jnl
Bit-Error and Soft-Error Resilient 7T/14T SRAM with 150-nm FD-SOI Process.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Shusuke Yoshimoto, Takuro Amashita, Shunsuke Okumura, Koji Nii, Masahiko Yoshimoto, Hiroshi Kawaguchi
2012 J jnl
Low-energy block-level instantaneous comparison 7T SRAM for dual modular redundancy.
IEICE Electron. Express
Shunsuke Okumura, Yohei Nakata, Koji Yanagida, Yuki Kagiyama, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto
2012 J jnl
Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure.
IEICE Trans. Electron.
Shusuke Yoshimoto, Takuro Amashita, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto
2012 — conf
Processor Coupling Architecture for Aggressive Voltage Scaling on Multicores.
ARCS Workshops
Koji Kugata, Shinpei Soda, Yohei Nakata, Shunsuke Okumura, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
2011 — conf
0.45-V operating Vt-variation tolerant 9T/18T dual-port SRAM.
ISQED
Hiroki Noguchi, Shunsuke Okumura, Tomoya Takagi, Koji Kugata, Masahiko Yoshimoto, Hiroshi Kawaguchi
2011 — conf
256-KB associativity-reconfigurable cache with 7T/14T SRAM for aggressive DVS down to 0.57 V.
ICECS
Jinwook Jung, Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto
2011 J jnl
7T SRAM Enabling Low-Energy Instantaneous Block Copy and Its Application to Transactional Memory.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Shunsuke Okumura, Yuki Kagiyama, Yohei Nakata, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto
2011 — conf
A 128-bit chip identification generating scheme exploiting SRAM bitcells with failure rate of 4.45 × 10
ESSCIRC
Shunsuke Okumura, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto
2011 — conf
Block-basis on-line BIST architecture for embedded SRAM using wordline and bitcell voltage optimal control.
ISQED
Masahiro Yoshikawa, Shunsuke Okumura, Yohei Nakata, Yuki Kagiyama, Hiroshi Kawaguchi, Masahiko Yoshimoto
2011 J jnl
Design Choice in 45-nm Dual-Port SRAM - 8T, 10T Single End, and 10T Differential.
Inf. Media Technol.
Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Shunsuke Okumura, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
2011 J jnl
Design Choice in 45-nm Dual-Port SRAM - 8T, 10T Single End, and 10T Differential.
IPSJ Trans. Syst. LSI Des. Methodol.
Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Shunsuke Okumura, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
2011 — conf
Low-power block-level instantaneous comparison 7T SRAM for dual modular redundancy.
CICC
Shunsuke Okumura, Yohei Nakata, Koji Yanagida, Yuki Kagiyama, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto
2011 — conf
Model-based fault injection for failure effect analysis - Evaluation of dependable SRAM for vehicle control units.
DSN Workshops
Yohei Nakata, Yasuhiro Ito, Yasuo Sugure, Shigeru Oho, Yusuke Takeuchi, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto
2011 J jnl
Session Initiation Protocol (SIP) Usage of the Offer/Answer Model.
RFC
Shunsuke Okumura, Takuya Sawada, Paul H. Kyzivat
2010 A conf
0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAM.
ISLPED
Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto
2010 — conf
7T SRAM enabling low-energy simultaneous block copy.
CICC
Shunsuke Okumura, Shusuke Yoshimoto, Kosuke Yamaguchi, Yohei Nakata, Hiroshi Kawaguchi, Masahiko Yoshimoto
2009 — conf
A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme.
ISQED
Shunsuke Okumura, Yusuke Iguchi, Shusuke Yoshimoto, Hidehiro Fujiwara, Hiroki Noguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
2009 Misc conf
A 7T/14T Dependable SRAM and its Array Structure to Avoid Half Selection.
VLSI Design
Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2009 J jnl
A Dependable SRAM with 7T/14T Memory Cells.
IEICE Trans. Electron.
Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto
2008 J jnl
A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing.
IEICE Trans. Electron.
Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Shunsuke Okumura, Yasuhiro Morita, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
2008 — conf
Quality of a Bit (QoB): A New Concept in Dependable SRAM.
ISQED
Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto