Shunli Ma - RankMe

56 papers C 5Journal 18Unranked 33

Year	Rank	Type	Title / Venue / Authors
2025	C	`conf`	A 4.8dB NF, 3-to-119GHz Distributed LNA With Three-Turn Transformer and Multiple Magnetic Coupling Feedback Network in 28nm CMOS. ISCAS Yujia Wang, Jincheng Zhang, Shunli Ma, Junyan Ren
2025	J	`jnl`	A Harmonic-Suppressed GaN Power Amplifier Using Artificial Coupled Resonator. IEEE Trans. Very Large Scale Integr. Syst. Letian Guo, Jincheng Zhang, Lihe Nie, Jian Wang, Yong Chen, Junyan Ren, Shunli Ma
2024	—	`conf`	NeuroSORT: A Neuromorphic Accelerator for Spike-based Online and Real-time Tracking. AICAS Ziyang Shen, Xiaoxu Xie, Chaoming Fang, Fengshi Tian, Shunli Ma, Jie Yang, Mohamad Sawan
2023	—	`conf`	A 15GHz Class-C VCO with Two-stage Buffer in 0.15-μm GaAs. ASICON Lei Wu, Junyan Ren, Tianxiang Wu, Shunli Ma
2023	—	`conf`	A 300MS/s 57.6dB SNDR Single-Channel SAR ADC with Accelerated SAR Logic. ASICON Muxi Zou, Shunli Ma, Xiaodi Feng, Junyan Ren, Tianxiang Wu
2023	J	`jnl`	A 4.5-W, 18.5-24.5-GHz GaN Power Amplifier Employing Chebyshev Matching Technique. IEEE Trans. Very Large Scale Integr. Syst. Yujia Wang, Jincheng Zhang, Yong Chen, Junyan Ren, Shunli Ma
2023	J	`jnl`	A 40nm 2TOPS/W Depth-Completion Neural Network Accelerator SoC With Efficient Depth Engine for Realtime LiDAR Systems. IEEE Trans. Circuits Syst. II Express Briefs Miao Sun, Yingjie Cao, Jian Qian, Jie Li, Sifan Zhou, Ziyu Zhao, Yifan Wu, Tao Xia, Yajie Qin, Lei Qiu, Shunli Ma, Patrick Yin Chiang, Shenglong Zhuo
2023	J	`jnl`	A 90- to 115-GHz superheterodyne receiver front-end for W-band imaging system in 28-nm complementary metal-oxide-semiconductor. Int. J. Circuit Theory Appl. Xi Wang, Dong Wei, Zhiyang Zhang, Tianxiang Wu, Xu Chen, Yong Chen, Junyan Ren, Shunli Ma
2023	—	`conf`	A High Gain and Wide Bandwidth Dual-Power CMOS Op-amp for High-Speed ADCs Application. ASICON Xiaodi Feng, Shunli Ma, Muxi Zou, Tianxiang Wu
2023	—	`conf`	A Multi-channel 12-bits 100MS/s SAR ADC in 65nm CMOS. ASICON Yigang Wei, Tianxiang Wu, Shunli Ma, Junyan Ren
2023	—	`conf`	An Improved Delay Cell with Low Power Consumption and Strong Driving Capability. ASICON Cai Tian, Tianxiang Wu, Shunli Ma, Wenzhong Bao
2023	—	`conf`	High Performance Bootstrap Switch for 14 bit SAR ADC with Redundancy in SMIC 180nm. ASICON Jing Yuan, Wenzhong Bao, Tianxiang Wu, Shunli Ma
2022	J	`jnl`	A 10-MHz to 50-GHz low-jitter multiphase clock generator for high-speed oscilloscope in 0.15-μm GaAs technology. Int. J. Circuit Theory Appl. Tianxiang Wu, Xi Wang, Yong Chen, Junyan Ren, Shunli Ma
2022	—	`conf`	A 134-154 GHz Low-Noise Amplifier Achieving 36.3-dB Maximum Gain with 3.8-dB Minimum Noise Figure for D-Band Imaging System. MWSCAS Xi Wang, Zhiyang Zhang, Junyan Ren, Shunli Ma
2022	J	`jnl`	A 23- to 28-GHz 5-bit switch-type phase shifter with 1-bit calibration based on optimized ABCD matrix design methods for 5G MIMO system in 0.15-μm GaAs. Int. J. Circuit Theory Appl. Zhiyang Zhang, Lihe Nie, Jincheng Zhang, Tianxiang Wu, Yong Chen, Junyan Ren, Shunli Ma
2022	—	`conf`	A 26-38GHz Ultra-Wideband Balanced Frequency Doubler in 0.15µ m GaAs pHEMT Process. APCCAS Wenyang Liu, Tianxiang Wu, Tianyang Yan, Fan Yang, Yong Chen, Shunli Ma
2022	J	`jnl`	A 6.5-mm IEEE Trans. Circuits Syst. II Express Briefs Jincheng Zhang, Lihe Nie, Yong Chen, Junyan Ren, Shunli Ma
2022	—	`conf`	A 60-GHz CMOS Balanced Power Amplifier with Miniaturized Quadrature Hybrids Achieving 19.0-dBm Output Power and 24.4% Peak PAE. APCCAS Zhiyang Zhang, Xi Wang, Yong Chen, Junyan Ren, Shunli Ma
2022	C	`conf`	A Two-Way Current-Combining W-band Power Amplifier Achieving 17.4-dBm Output Power with 19.4% PAE in 65-nm Bulk CMOS. ISCAS Zhiyang Zhang, Xi Wang, Junyan Ren, Shunli Ma
2022	J	`jnl`	Promise Σ-protocol: How to Construct Efficient Threshold ECDSA from Encryptions Based on Class Groups. IACR Cryptol. ePrint Arch. Yi Deng, Shunli Ma, Xinxuan Zhang, Hailong Wang, Xuyang Song, Xiang Xie
2021	J	`jnl`	A 120-150 GHz Power Amplifier in 28-nm CMOS Achieving 21.9-dB Gain and 11.8-dBm P IEEE Access Jincheng Zhang, Tianxiang Wu, Lihe Nie, Shunli Ma, Yong Chen, Junyan Ren
2021	—	`conf`	A 3-to-78GHz Differential Distributed Amplifier with Ultra- Balanced Active Balun and Gain Boosting Techniques in 65-nm CMOS Process. A-SSCC Jincheng Zhang, Tianxiang Wu, Yong Chen, Junyan Ren, Shunli Ma
2021	—	`conf`	A 35-to-50 GHz CMOS Low-Noise Amplifier with 22.2% -1-dB Fractional Bandwidth and 30.5-dB Maximum Gain for 5G New Radio. ESSCIRC Dong Wei, Tianxiang Wu, Shunli Ma, Yong Chen, Junyan Ren
2021	J	`jnl`	A 5G Wireless Event-Driven Sensor Chip for Online Power-Line Disturbances Detecting Network in 0.25 μm GaAs Process. IEEE Trans. Ind. Electron. Shunli Ma, Tianxiang Wu, Jincheng Zhang, Junyan Ren
2021	J	`jnl`	A 6.94-fJ/Conversion-Step 12-bit 100-MS/s Asynchronous SAR ADC Exploiting Split-CDAC in 65-nm CMOS. IEEE Access Manxin Li, Yuting Yao, Biao Hu, Jipeng Wei, Yong Chen, Shunli Ma, Fan Ye, Junyan Ren
2021	—	`conf`	A 79GHz 5-bit Phase Shifter With π-Network in 28-nm CMOS. ASICON Xu Chen, Junyan Ren, Shunli Ma
2021	—	`conf`	A C-Band Power Amplifier with Over-Neutralization Technique and Coupled-Line MCR Matching Methods for 5G Communication in 0.25-μm GaAs. ASICON Zhiyang Zhang, Junyan Ren, Shunli Ma
2021	—	`conf`	An 4 ASICON Xi Wang, Junyan Ren, Shunli Ma
2021	J	`jnl`	An Efficient NIZK Scheme for Privacy-Preserving Transactions Over Account-Model Blockchain. IEEE Trans. Dependable Secur. Comput. Shunli Ma, Yi Deng, Debiao He, Jiang Zhang, Xiang Xie
2021	J	`jnl`	Analysis and Design of a 35-GHz Hybrid π-Network High-Gain Phase Shifter With 360° Continuous Phase Shifting. IEEE Access Dong Wei, Xuan Ding, Hai Yu, Yen-Cheng Kuan, Qun Jane Gu, Zhiwei Xu, Shunli Ma, Junyan Ren
2021	—	`conf`	Promise $\varSigma $-Protocol: How to Construct Efficient Threshold ECDSA from Encryptions Based on Class Groups. ASIACRYPT (4) Yi Deng, Shunli Ma, Xinxuan Zhang, Hailong Wang, Xuyang Song, Xiang Xie
2020	—	`conf`	A 10-18 GHz GaN Power Amplifier Based on Asymmetric Magnetically Coupled Resonator. MWSCAS Jincheng Zhang, Lihe Nie, Shunli Ma, Junyan Ren
2020	C	`conf`	A Practical NIZK Argument for Confidential Transactions over Account-Model Blockchain. ProvSec Shunli Ma, Yi Deng, Mengqiu Bai, Debiao He, Jiang Zhang, Xiang Xie
2020	J	`jnl`	A Quadrature PLL With Phase Mismatch Calibration for 32GS/s Time-Interleaved ADC. IEEE Access Shunli Ma, Tianxiang Wu, Junyan Ren
2020	J	`jnl`	Analog Integrated Circuits Based on Wafer-Level Two-Dimensional MoS IEEE Access Shunli Ma, Yan Wang, Xinyu Chen, Tianxiang Wu, Xi Wang, Hongwei Tang, Yuting Yao, Hao Yu, Yaochen Sheng, Jingyi Ma, Junyan Ren, Wenzhong Bao
2019	—	`conf`	A 130-150 GHz Power Amplifier for Millimeter Wave Imaging in 65-nm CMOS. ASICON Jincheng Zhang, Lihe Nie, Dong Wei, Tianxiang Wu, Shunli Ma, Junyan Ren
2019	—	`conf`	A 140 GHz, 4 dB Noise-Figure Low-Noise Amplifier Design with the Compensation of Parasitic Capacitance CGS. MWSCAS Dong Wei, Xuan Ding, Hai Yu, Bo Yu, Shunli Ma, Qun Jane Gu, Junyan Ren
2019	—	`conf`	A 22-40.5 GHz UWB LNA Design in 0.15um GaAs. ASICON Dong Wei, Jincheng Zhang, Tianxiang Wu, Shunli Ma, Junyan Ren
2019	—	`conf`	A 256MHz Analog Baseband Chain with tunable Bandwidth and Gain for UWB Receivers. ASICON Yuting Yao, Jipeng Wei, Manxin Li, Shunli Ma, Fan Ye, Junyan Ren
2019	—	`conf`	A 36-40 GHz VCO with bonding inductors for millimeter wave 5G Communication. ASICON Tianxiang Wu, Jincheng Zhang, Dong Wei, Lihe Nie, Yuting Yao, Shunli Ma, Junyan Ren
2019	J	`jnl`	A 5-10-Gb/s 12.5-mW Source Synchronous I/O Interface With 3-D Flip Chip Package. IEEE Trans. Circuits Syst. I Regul. Pap. Shunli Ma, Hao Yu, Qun Jane Gu, Junyan Ren
2019	C	`conf`	A Novel Nauta Transconductor for Ultra-Wideband gm-C Filter with Temperature Calibration. ISCAS Jipeng Wei, Yuting Yao, Longheng Luo, Shunli Ma, Fan Ye, Junyan Ren
2019	—	`conf`	SPICE Modeling and Simulation of High-Performance Wafer-Scale MoS2 Transistors. ASICON Yuting Yao, Manxin Li, Tianxiang Wu, Hu Xu, Shunli Ma, Wenzhong Bao, Junyan Ren
2018	J	`jnl`	A 5-to-8-GHz Wideband Miniaturized Dielectric Spectroscopy Chip With $I/Q$ Mismatch Calibration in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. Shunli Ma, Ning Li, Junyan Ren
2017	—	`conf`	A 7GHz-bandwidth 31.5 GHz FMCW-PLL with novel twin-VCOs structure in 65nm CMOS. A-SSCC Shunli Ma, Jili Sheng, Ning Li, Junyan Ren
2017	J	`jnl`	An Efficient NIZK Scheme for Privacy-Preserving Transactions over Account-Model Blockchain. IACR Cryptol. ePrint Arch. Shunli Ma, Yi Deng, Debiao He, Jiang Zhang, Xiang Xie
2015	—	`conf`	A 30-GHz to 39-GHz mm-Wave low-power injection-locked frequency divider in 65nm CMOS. ASICON Guangyao Zhou, Shunli Ma, Fazhi An, Ning Li, Fan Ye, Junyan Ren
2015	—	`conf`	A 39 GHz-80 GHz millimeter-wave frequency doubler with low power consumption in 65nm CMOS tehnology. ASICON Qian Chen, Fazhi An, Guangyao Zhou, Shunli Ma, Fan Ye, Junyan Ren
2015	—	`conf`	A quadrature clock generator with calibration for 22∼31.4 GS/s real-time sampling system. ESSCIRC Shunli Ma, Guangyao Zhou, Jianbing Jiang, Chixiao Chen, Yongzhen Chen, Fan Ye, Junyan Ren
2015	—	`conf`	A wide-division-ratio 100MHz-to-5GHz multi-modulus divider chain for wide-band PLL. ASICON Fazhi An, Shunli Ma, Qian Chen, Guangyao Zhou, Fan Ye, Junyan Ren
2014	—	`conf`	A 131.5GHz, -84dBm sensitivity super-regenerative receiver by zero-phase-shifter coupled oscillator network in 65nm CMOS. ESSCIRC Shunli Ma, Hao Yu, Yang Shang, Wei Meng Lim, Junyan Ren
2014	C	`conf`	A 400-MS/s 8-b 2-b/cycle SAR ADC with shared interpolator and alternative comparators. ISCAS Guoxian Dai, Chixiao Chen, Shunli Ma, Fan Ye, Junyan Ren
2014	—	`conf`	An overview of new design techniques for high performance CMOS millimeter-wave circuits. ISIC Shunli Ma, Junyan Ren, Hao Yu
2013	—	`conf`	A 75.7GHz to 102GHz rotary-traveling-wave VCO by tunable composite right /left hand T-line. CICC Shunli Ma, Wei Fei, Hao Yu, Junyan Ren
2013	—	`conf`	High-speed and low-power 2.5D I/O circuits for memory-logic-integration by through-silicon interposer. 3DIC Jiacheng Wang, Shunli Ma, Sai Manoj Pudukotai Dinakarrao, Mingbin Yu, Roshan Weerasekera, Hao Yu
2012	—	`conf`	A low power programmable band-pass filter with novel pseudo-resistor for portable biopotential acquisition system. APCCAS Shunli Ma, Changming Chen, Yiwen Zhang, Junyan Ren