Shunichi Toida

15 papers C 1Misc 4Journal 8Unranked 1
YearRankTypeTitle / Venue / Authors
2006 C conf
Preposition Senses: Generalized Disambiguation Model.
CICLing
Chutima Boonthum, Shunichi Toida, Irwin B. Levinstein
1994 J jnl
On Polynomial-Time Testable Combinational Circuits.
IEEE Trans. Computers
Nageswara S. V. Rao, Shunichi Toida
1993 Misc conf
Revisiting shift register realization for ease of test generation and testing.
VTS
Shunichi Toida
1992 Misc conf
Computational Complexity of Test-Point Insertions and Decompositions.
VLSI Design
Nageswara S. V. Rao, Shunichi Toida
1992 Misc conf
On test generation for combinational circuits consisting of AND and EXOR gates.
VTS
Shunichi Toida, Nageswara S. V. Rao
1991 Misc conf
On polynomial-time testable classes of combinational circuits.
VTS
Nageswara S. V. Rao, Shunichi Toida
1982 J jnl
The Complexity of Fault Detection Problems for Combinational Logic Circuits.
IEEE Trans. Computers
Hideo Fujiwara, Shunichi Toida
1981 J jnl
On Minimal Test Sets for Locating Single Link Failures in Networks.
IEEE Trans. Computers
Toshihide Ibaraki, Tsunehiko Kameda, Shunichi Toida
1977 J jnl
A note on Ádám's conjecture.
J. Comb. Theory B
Shunichi Toida
1976 J jnl
System Diagnosis and Redundant Tests.
IEEE Trans. Computers
Shunichi Toida
1975 J jnl
A Diagnosing Algorithm for Networks
Inf. Control.
Tiko Kameda, Shunichi Toida, F. J. Allan
1975 J jnl
An Approach to the Diagnosability Analysis of a System.
IEEE Trans. Computers
F. J. Allan, Tiko Kameda, Shunichi Toida
1973 — conf
Efficient Algorithms for Determining an Extremal Tree of a Graph (Extended Abstract)
SWAT
Tiko Kameda, Shunichi Toida
1973 J jnl
Generation of all Cutsets of a Bipath Network.
IEEE Trans. Commun.
Shunichi Toida
1969 — —
A Characterization of Biplanar Graphs
Shunichi Toida