Shunichi Kaeriyama

11 papers Journal 6Unranked 5

Year	Rank	Type	Title / Venue / Authors
2015	—	`conf`	Session 3 overview: Ultra-high-speed wireline transceivers and energy-efficient links: Wireline subcommittee. ISSCC Ken Chang, Shunichi Kaeriyama
2012	J	`jnl`	A 2.5 kV Isolation 35 kV/us CMR 250 Mbps Digital Isolator in Standard CMOS With a Small Transformer Driving Technique. IEEE J. Solid State Circuits Shunichi Kaeriyama, Shinichi Uchida, Masayuki Furumiya, Mitsuji Okada, Tadashi Maeda, Masayuki Mizuno
2012	—	`conf`	High-speed wireline transceivers and clocking. CICC Gerrit den Besten, Shunichi Kaeriyama
2011	J	`jnl`	A Clock Generator with Clock Period, Duty-Ratio and I/Q-Balance Adjustment Capabilities for On-Chip Timing-Margin Tests. IEICE Trans. Electron. Shunichi Kaeriyama, Mikihiro Kajita, Masayuki Mizuno
2009	J	`jnl`	A 40 Gb/s Multi-Data-Rate CMOS Transmitter and Receiver Chipset With SFI-5 Interface for Optical Transmission Systems. IEEE J. Solid State Circuits Shunichi Kaeriyama, Yasushi Amamiya, Hidemi Noguchi, Zin Yamazaki, Tomoyuki Yamase, Ken'ichi Hosoya, Minoru Okamoto, Shiro Tomari, Hiroshi Yamaguchi, Hiroaki Shoda, Hironobu Ikeda, Shinji Tanaka, Tsugio Takahashi, Risato Ohhira, Arihide Noda, Ken'ichiro Hijioka, Akira Tanabe, Sadao Fujita, Nobuhiro Kawahara
2009	—	`conf`	A 40Gb/s multi-data-rate CMOS transceiver chipset with SFI-5 interface for optical transmission systems. ISSCC Yasushi Amamiya, Shunichi Kaeriyama, Hidemi Noguchi, Zin Yamazaki, Tomoyuki Yamase, Ken'ichi Hosoya, Minoru Okamoto, Shiro Tomari, Hiroshi Yamaguchi, Hiroaki Shoda, Hironobu Ikeda, Shinji Tanaka, Tsugio Takahashi, Risato Ohhira, Arihide Noda, Ken'ichiro Hijioka, Akira Tanabe, Sadao Fujita, Nobuhiro Kawahara
2007	—	`conf`	A 1-to-2GHz 4-Phase On-Chip Clock Generator with Timing-Margin Test Capability. ISSCC Shunichi Kaeriyama, Mikihiro Kajita, Masayuki Mizuno
2006	J	`jnl`	Solid-Electrolyte Nanometer Switch. IEICE Trans. Electron. Naoki Banno, Toshitsugu Sakamoto, Noriyuki Iguchi, Hisao Kawaura, Shunichi Kaeriyama, Masayuki Mizuno, Kazuya Terabe, Tsuyoshi Hasegawa, Masakazu Aono
2005	J	`jnl`	A nonvolatile programmable solid-electrolyte nanometer switch. IEEE J. Solid State Circuits Shunichi Kaeriyama, Toshitsugu Sakamoto, Hiroshi Sunamura, Masayuki Mizuno, Hisao Kawaura, Tsuyoshi Hasegawa, Kazuya Terabe, Tomonobu Nakayama, Masakazu Aono
2005	J	`jnl`	Logic-in-Memory VLSI circuit for Fully Parallel Nearest Pattern Matching Based on Floating-Gate-MOS Pass-Transistor Logic. J. Multiple Valued Log. Soft Comput. Takahiro Hanyu, Shunichi Kaeriyama, Michitaka Kameyama
2000	—	`conf`	Arithmetic-Oriented Multiple-Valued Logic-in-Memory VLSI Based on Current-Mode Logic. ISMVL Shunichi Kaeriyama, Takahiro Hanyu, Michitaka Kameyama