Shun-Wen Cheng

18 papers B 1Journal 4Unranked 13
YearRankTypeTitle / Venue / Authors
2024 J jnl
Changes in Navigation Controls and Field-of-View Modes Affect Cybersickness Severity and Spatiotemporal Gait Patterns After Exposure to Virtual Environments.
Hum. Factors
Ming-I Brandon Lin, Bonnie Wu, Shun-Wen Cheng
2018 — conf
Universal CMOS Diamond-Graph Circuit for Embedded Computing.
SoCC
Shun-Wen Cheng, Chun-Pin Lin, Chi-Shi Chen, Wei-Chang Tsai
2016 — conf
A driver's physiological monitoring system based on photodiode sensor with reflective optics element.
ICVES
Chun-Yao Shih, Shun-Wen Cheng
2016 — conf
Self-dual diamond-graph CMOS H-bridge logic family.
SoCC
Shun-Wen Cheng
2014 B conf
Opportunities for Persuasive Technology to Motivate Heavy Computer Users for Stretching Exercise.
PERSUASIVE
Yong-Xiang Chen, Siek-Siang Chiang, Shu-Yun Chih, Wen-Ching Liao, Shih-Yao Lin, Shang-Hua Yang, Shun-Wen Cheng, Shih-Sung Lin, Yu-Shan Lin, Ming-Sui Lee, Jau-Yih Tsauo, Cheng-Min Jen, Chia-Shiang Shih, King-Jen Chang, Yi-Ping Hung
2010 — conf
Over complementary MOS logic for don't care conditions.
APCCAS
Shun-Wen Cheng
2008 — conf
H-tree CMOS logic circuit.
ICECS
Shun-Wen Cheng
2006 J jnl
64-bit Pipeline Carry Lookahead Adder Using all-n-transistor Tspc Logics.
J. Circuits Syst. Comput.
Kuo-Hsing Cheng, Shun-Wen Cheng, Wen-Shiuan Lee
2006 J jnl
Improved 32-bit Conditional Sum Adder for Low-Power High-Speed Applications.
J. Inf. Sci. Eng.
Kuo-Hsing Cheng, Shun-Wen Cheng
2005 J jnl
64-Bit High-Performance Power-Aware Conditional Carry Adder Design.
IEICE Trans. Electron.
Kuo-Hsing Cheng, Shun-Wen Cheng
2004 — conf
64-bit Hybrid Dual-Threshold Voltage Power-Aware Conditional Carry Adder Design.
IWSOC
Kuo-Hsing Cheng, Shun-Wen Cheng, Chan-Wei Huang
2004 — conf
64-bit Low Threshold Voltage High-Speed Conditional Carry Adder by Complementary Pass-Transistor Logi.
ISVLSI
Kuo-Hsing Cheng, Shun-Wen Cheng, Che-Yu Liao
2003 — conf
A high-speed magnitude comparator with small transistor count.
ICECS
Shun-Wen Cheng
2003 — conf
Arbitrary long digit integer sorter HW/SW co-design.
ASP-DAC
Shun-Wen Cheng
2002 — conf
Influences of minimum cut plane properties on the mincut circuit partitioning problems.
ICECS
Kuo-Hsing Cheng, Shun-Wen Cheng
2002 — conf
Prioritized Prime Implicant Patterns Puzzle for Novel Logic Synthesis and Optimization.
ASP-DAC/VLSI Design
Kuo-Hsing Cheng, Shun-Wen Cheng
2001 — conf
A study on the relationship between initial node-edge pairs entropy and mincut circuit partitioning.
ICECS
Kuo-Hsing Cheng, Shun-Wen Cheng
2001 — conf
ENISLE: an intuitive heuristic nearly optimal solution for mincut and ratio mincut partitioning.
ISCAS (5)
Shun-Wen Cheng, Kuo-Hsing Cheng