Shuli Gao

18 papers C 1Journal 8Unranked 9
YearRankTypeTitle / Venue / Authors
2025 J jnl
PromoGuardian: Detecting Promotion Abuse Fraud with Multi-Relation Fused Graph Neural Networks.
CoRR
Shaofei Li, Xiao Han, Ziqi Zhang, Minyao Hua, Shuli Gao, Zhenkai Liang, Yao Guo, Xiangqun Chen, Ding Li
2017 — conf
Decimal floating-point multiplier with binary-decimal compression based fixed-point multiplier.
CCECE
Shuli Gao, Dhamin Al-Khalili, J. M. Pierre Langlois, Noureddine Chabini
2017 J jnl
Efficient Realization of BCD Multipliers Using FPGAs.
Int. J. Reconfigurable Comput.
Shuli Gao, Dhamin Al-Khalili, J. M. Pierre Langlois, Noureddine Chabini
2017 — conf
Random channel generator of the integrated power line communication and visible light communication.
ISPLC
Shuli Gao, Jian Zhang, Jian Song, Hui Yang, Xi Chu
2016 J jnl
Factors affecting the performance of knowledge collaboration in virtual team based on capital appreciation.
Inf. Technol. Manag.
Shuli Gao, Yanli Guo, Jianbin Chen, Lin Li
2014 — conf
FPGA implementation of multiple Pursuit-Evasion games with decentralized Learning Automata.
SysCon
Shuli Gao, Sidney N. Givigi, Alain J. G. Beaulieu
2012 — conf
An improved BCD adder using 6-LUT FPGAs.
NEWCAS
Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini
2012 J jnl
Asymmetric large size multipliers with optimised FPGA resource utilisation.
IET Comput. Digit. Tech.
Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini, J. M. Pierre Langlois
2011 J jnl
A Highly Sensitive and Selective Competition Assay for the Detection of Cysteine Using Mercury-Specific DNA, Hg
Sensors
Hui Xu, Shuli Gao, Quanwen Liu, Dun Pan, Lihua Wang, Shuzhen Ren, Min Ding, Jingwen Chen, Gang Liu
2011 — conf
Asymmetric Large Size Signed Multipliers Using Embedded Blocks in FPGAs.
IPDPS Workshops
Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini
2011 — conf
Asymmetric large size multiplication using embedded blocks with efficient compression technique in FPGAs.
ICECS
Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini
2010 J jnl
FPGA-Based Efficient Design Approaches for Large Size Two's Complement Squarers.
J. Signal Process. Syst.
Shuli Gao, Noureddine Chabini, Dhamin Al-Khalili, J. M. Pierre Langlois
2009 J jnl
Efficient Scheme for Implementing Large Size Signed Multipliers Using Multigranular Embedded DSP Blocks in FPGAs.
Int. J. Reconfigurable Comput.
Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini
2009 — conf
Two level decomposition based matrix multiplication for FPGAs.
ICECS
Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini
2007 — conf
FPGA-Based Efficient Design Approach for Large-Size Two's Complement Squarers.
ASAP
Shuli Gao, Noureddine Chabini, Dhamin Al-Khalili, J. M. Pierre Langlois
2007 J jnl
Optimised realisations of large integer multipliers and squarers using embedded blocks.
IET Comput. Digit. Tech.
Shuli Gao, Noureddine Chabini, Dhamin Al-Khalili, J. M. Pierre Langlois
2006 C conf
An Optimized Design Approach for Squaring Large Integers Using Embedded Hardwired Multipliers.
AICCSA
Shuli Gao, Noureddine Chabini, Dhamin Al-Khalili, J. M. Pierre Langlois
2006 — conf
Efficient FPGA-Based Realization of Complex Squarer and Complex Conjugate using Embedded Multipliers.
SoCC
Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini, J. M. Pierre Langlois