Shuji Tsukiyama

47 papers A* 2A 1C 2Journal 17Unranked 24

Year	Rank	Type	Title / Venue / Authors
2019	C	`conf`	Gaussian Mixture Reduction Methods Using Support Vector Machine. TENCON Haruki Kazama, Shuji Tsukiyama
2017	J	`jnl`	A New Algorithm to Determine Covariance in Statistical Maximum for Gaussian Mixture Model. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Daiki Azuma, Shuji Tsukiyama
2017	—	`conf`	Approximating the maximum of Gaussians by a Gaussian mixture model for statistical designs. ECCTD Daiki Azuma, Shuji Tsukiyama, Masahiro Fukui
2016	J	`jnl`	A New Algorithm for Reducing Components of a Gaussian Mixture Model. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Naoya Yokoyama, Daiki Azuma, Shuji Tsukiyama, Masahiro Fukui
2015	—	`conf`	A statistical method for analyzing lifetime of a series-connected battery cells. ISCIT Daisuke Sasaki, Shuji Tsukiyama, Mariko Matsunaga, Junichi Miyamoto, Shingo Takahashi
2013	J	`jnl`	A New Delay Distribution Model with a Half Triangular Distribution for Statistical Static Timing Analysis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shuji Tsukiyama, Masahiro Fukui
2013	—	`conf`	A new delay distribution model to take long-term degradation into account. LASCAS Shuji Tsukiyama, Masahiro Fukui, Takashi Kambe
2013	—	`conf`	An implementation and evaluation of Backward Euler algorithm to GPGPU power grid circuit simulation. NEWCAS Lei Lin, Masahiro Fukui, Shuji Tsukiyama
2013	—	`conf`	Application-specific arithmetic circuit design for a particle tracking application. LASCAS Takashi Kambe, Kohsei Takehara, Shuji Tsukiyama
2011	J	`jnl`	A Statistical Maximum Algorithm for Gaussian Mixture Models Considering the Cumulative Distribution Function Curve. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shuji Tsukiyama, Masahiro Fukui
2011	—	`conf`	A new statistical maximum operation for Gaussian mixture models and its evaluations. ECCTD Shuji Tsukiyama, Masahiro Fukui
2011	—	`conf`	A power grid optimization algorithm considering timing degradation by NBTI. ISOCC Masahiro Fukui, Yoriaki Nagata, Shuji Tsukiyama
2011	—	`conf`	A power grid optimization algorithm considering via reliability. ECCTD Masahiro Fukui, Haruo Miki, Masaya Yoshikawa, Shuji Tsukiyama
2011	A	`conf`	An algorithm to improve accuracy of criticality in statistical static timing analysis. DATE Shuji Tsukiyama, Masahiro Fukui
2011	—	`conf`	An automatic layout method for timing pulse generator of small LCD driver. ECCTD Shohei Asakawa, Shuji Tsukiyama, Isao Shirakawa, Shuji Nishi, Tadashi Takeda, Tomoyuki Nagai, Yasushi Kubota
2009	A*	`conf`	A Gaussian mixture model for statistical timing analysis. DAC Shingo Takahashi, Yuki Yoshida, Shuji Tsukiyama
2009	J	`jnl`	A New Statistical Timing Analysis Using Gaussian Mixture Models for Delay and Slew Propagated Together. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shingo Takahashi, Shuji Tsukiyama
2009	—	`conf`	A new power grid optimization algorithm based on manufacturing cost restriction. ECCTD Takayuki Hayashi, Masahiro Fukui, Shuji Tsukiyama
2009	—	`conf`	Accuracy of the criticality probabilty of a path in statistical timing analysis. ECCTD Shuji Tsukiyama, Masahiro Fukui
2008	J	`jnl`	A Power Grid Optimization Algorithm by Observing Timing Error Risk by IR Drop. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yoshiyuki Kawakami, Makoto Terao, Masahiro Fukui, Shuji Tsukiyama
2008	—	`conf`	A new statistical timing analyzer propagating delay and slew distributions simultaneously. APCCAS Shingo Takahashi, Shuji Tsukiyama
2007	J	`jnl`	Transistor Sizing of LCD Driver Circuit for Technology Migration. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masanori Hashimoto, Takahito Ijichi, Shingo Takahashi, Shuji Tsukiyama, Isao Shirakawa
2006	J	`jnl`	A Sampling Switch Design Procedure for Active Matrix Liquid Crystal Displays. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shingo Takahashi, Shuji Tsukiyama, Masanori Hashimoto, Isao Shirakawa
2006	J	`jnl`	An Algorithm to Calculate Correlation Coefficients between Interconnect Delays for Use in Statistical Timing Analysis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shuji Tsukiyama, Masahiko Tomita
2006	C	`conf`	An algorithm for calculating correlation coefficients between Elmore interconnect delays. ISCAS Shuji Tsukiyama, Masahiko Tomita
2005	—	`conf`	A design scheme for sampling switch in active matrix LCD. ECCTD Shingo Takahashi, Akira Taji, Shuji Tsukiyama, Masanori Hashimoto, Isao Shirakawa
2005	—	`conf`	Interconnect capacitance extraction for system LCD circuits. ACM Great Lakes Symposium on VLSI Yoshihiro Uchida, Sadahiro Tani, Masanori Hashimoto, Shuji Tsukiyama, Isao Shirakawa
2004	—	`conf`	Toward stochastic design for digital circuits: statistical static timing analysis. ASP-DAC Shuji Tsukiyama
2003	J	`jnl`	Parasitic Capacitance Modeling for Non-Planar Interconnects in Liquid Crystal Displays. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Sadahiro Tani, Yoshihiro Uchida, Makoto Furuie, Shuji Tsukiyama, BuYeol Lee, Shuji Nishi, Yasushi Kubota, Isao Shirakawa, Shigeki Imai
2002	—	`conf`	Parasitic capacitance modeling for multilevel interconnects. APCCAS (1) Sadahiro Tani, Yoshihiro Uchida, Makoto Furuie, Shuji Tsukiyama, BuYeol Lee, Shuji Nishi, Yasushi Kubota, Isao Shirakawa, Shigeki Imai
2001	—	`conf`	A statistical static timing analysis considering correlations between delays. ASP-DAC Shuji Tsukiyama, Masakazu Tanaka, Masahiro Fukui
2001	—	`conf`	Two-dimensional array layout for NMOS 4-phase dynamic logic. ICECS Makoto Furuie, Takao Onoye, Shuji Tsukiyama, Isao Shirakawa
2000	—	`conf`	An interconnect topology optimization by a tree transformation. ASP-DAC Naofumi Tsujii, Katsutoshi Baba, Shuji Tsukiyama
1997	—	`conf`	Not necessarily more switches more routability [sic.]. ASP-DAC Yu-Liang Wu, Douglas Chang, Malgorzata Marek-Sadowska, Shuji Tsukiyama
1996	J	`jnl`	Graph based analysis of 2-D FPGA routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yu-Liang Wu, Shuji Tsukiyama, Malgorzata Marek-Sadowska
1995	—	`conf`	A hybrid hierarchical approach for multi-layer global routing. ED&TC Masayuki Hayashi, Shuji Tsukiyama
1994	—	`conf`	On computational complexity of a detailed routing problem in two dimensional FPGAs. Great Lakes Symposium on VLSI Yu-Liang Wu, Shuji Tsukiyama, Malgorzata Marek-Sadowska
1993	—	`ch.`	An Algorithm to Eliminate All Complex Triangles in a Maximal Planar Graph for Use in VLSI floorplan. Algorithmic Aspects of VLSI Layout Shuji Tsukiyama, Keiichi Koike, Isao Shirakawa
1992	—	`conf`	A distributed routing system for multilayer SOG. EURO-DAC Takashi Shimamoto, Hidetaka Hane, Isao Shirakawa, Shuji Tsukiyama, Shoji Shinoda, Nobuyasu Yui, Nobuyuki Nishiguchi
1991	J	`jnl`	On area-efficient drawings of rectangular duals for VLSI floor-plan. Math. Program. Katsunori Tani, Shuji Tsukiyama, Shoji Shinoda, Isao Shirakawa
1983	J	`jnl`	A New Global Router for Gate Array LSIsi. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shuji Tsukiyama, Ikuo Harada, Masahiro Fukui, Isao Shirakawa
1983	J	`jnl`	On the Layering Problem of Multilayer PWB Wiring. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shuji Tsukiyama, Ernest S. Kuh, Isao Shirakawa
1982	J	`jnl`	Double-row planar routing and permutation layout. Networks Shuji Tsukiyama, Ernest S. Kuh
1981	A*	`conf`	On the layering problem of multilayer PWB wiring. DAC Shuji Tsukiyama, Ernest S. Kuh, Isao Shirakawa
1980	J	`jnl`	An Algorithm to Enumerate All Cutsets of a Graph in Linear Time per Cutset. J. ACM Shuji Tsukiyama, Isao Shirakawa, Hiroshi Ozaki, Hiromu Ariyoshi
1980	—	`conf`	On the layering problem of multilayer PWB wiring. Graph Theory and Algorithms Shuji Tsukiyama, Ernest S. Kuh, Isao Shirakawa
1977	J	`jnl`	A New Algorithm for Generating All the Maximal Independent Sets. SIAM J. Comput. Shuji Tsukiyama, Mikio Ide, Hiromu Ariyoshi, Isao Shirakawa