Shuichi Sakai

123 papers A* 9A 11B 4C 17Misc 4Journal 31Unranked 47
YearRankTypeTitle / Venue / Authors
2026 J jnl
Inspex: Speculative Execution of Ready-to-Execute Loads in In-Order Cores.
IEEE Comput. Archit. Lett.
Yotaro Nada, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai
2025 B conf
Biotite: A High-Performance Static Binary Translator using Source-Level Information.
CC
Changbin Chen, Shu Sugita, Yotaro Nada, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya
2025 J jnl
Enhancing GPU Performance Through Complexity-Effective Out-of-Order Execution Using Distance-Based ISA.
IEICE Trans. Inf. Syst.
Reoma Matsuo, Toru Koizumi, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya
2025 J jnl
Flexible Approximate Computing for Mitigating Branch Divergence in GPUs.
IEEE Micro
Reoma Matsuo, Yuya Degawa, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya
2024 — conf
A Wireless Data and Power Transfer-Enabled MCU for Shape-Configurable Chiplet-Based Computers.
APCCAS
Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2024 — conf
Branch Divergence-Aware Flexible Approximating Technique on GPUs.
COOL CHIPS
Reoma Matsuo, Yuya Degawa, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya
2024 — conf
CommuTiles: Shape-Changeable Modular Computer System Using Proximity Wireless Communication.
CHI Extended Abstracts
Masato Goto, Ibuki Sugiyama, Kenta Higuchi, Toshiki Goto, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2024 J jnl
Cycle-Oriented Dynamic Approximation: Architectural Framework to Meet Performance Requirements.
IEEE Comput. Archit. Lett.
Yuya Degawa, Shota Suzuki, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2024 — conf
DataPipettor: Touch-Based Information Transfer Interface Using Proximity Wireless Communication.
UIST (Adjunct Volume)
Shoi To, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2024 C conf
Designing a Reactive Programming Language for Shape-Adaptive Computers.
APSEC
Yusuke Izawa, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2024 — conf
Multi-Tree Network Protocol Enabling System Partitioning for Shape-Changeable Computer System.
CF
Shun Nagasaki, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2024 J jnl
TURBULENCE: Complexity-Effective Out-of-Order Execution on GPU With Distance-Based ISA.
IEEE Comput. Archit. Lett.
Reoma Matsuo, Toru Koizumi, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya
2023 — conf
A Functional Reactive Programming Language for Wirelessly Connected Shape-Changeable Chiplet-Based Computers.
SPLASH Companion
Yusuke Izawa, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2023 J jnl
A Principal Factor of Performance in Decoupled Front-End.
IEICE Trans. Inf. Syst.
Yuya Degawa, Toru Koizumi, Tomoki Nakamura, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2023 B conf
A Sound and Complete Algorithm for Code Generation in Distance-Based ISA.
CC
Shu Sugita, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai
2023 C conf
An Out-of-Order Superscalar Processor Using STRAIGHT Architecture in 28 nm CMOS.
ISCAS
Taichi Amano, Junichiro Kadomoto, Satoshi Mitsuno, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai
2023 A* conf
Clockhands: Rename-free Instruction Set Architecture for Out-of-order Processors.
MICRO
Toru Koizumi, Ryota Shioya, Shu Sugita, Taichi Amano, Yuya Degawa, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2023 J jnl
Dynamically Reconfigurable Network Protocol for Shape-Changeable Computer System.
IEEE Des. Test
Shun Nagasaki, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2023 J jnl
FPGA-based Garbling Accelerator with Parallel Pipeline Processing.
IEICE Trans. Inf. Syst.
Rin Oishi, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2023 Misc conf
Poster Abstract: Investigation of Distance Sensing Method Using Magnetic Resonant Coupled Coils for Deformable User Interfaces.
SenSys
Kenta Higuchi, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2023 Misc conf
Poster Abstract: Towards a Tiny Digital Displacement Sensor Utilizing Bit-Error Characteristics of Inter-Chip Wireless Bus.
SenSys
Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2023 A conf
TURBULENCE: Complexity-effective Out-of-order Execution on GPU with Distance-based ISA.
DATE
Reoma Matsuo, Toru Koizumi, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya
2023 — conf
iKnowde: Interactive Learning Path Generation System Based on Knowledge Dependency Graphs.
UIST (Adjunct Volume)
Takashi Murayama, Shu Sugita, Hiroyuki Saegusa, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2022 — conf
Deformable Chiplet-Based Computer Using Inductively Coupled Wireless Communication.
ASP-DAC
Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2022 — conf
Evaluation of Different Microarchitectures for Energy-Efficient RISC-V Cores.
MCSoC
Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2022 A conf
T-SKID: Predicting When to Prefetch Separately from Address Prediction.
DATE
Toru Koizumi, Tomoki Nakamura, Yuya Degawa, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya
2021 C conf
Accurate and Fast Performance Modeling of Processors with Decoupled Front-end.
ICCD
Yuya Degawa, Toru Koizumi, Tomoki Nakamura, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2021 C conf
Compiling and Optimizing Real-world Programs for STRAIGHT ISA.
ICCD
Toru Koizumi, Shu Sugita, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2021 — conf
Multiport Register File Design for High-Performance Embedded Cores.
MCSoC
Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2021 C conf
Stochastic Iterative Approximation: Software/hardware techniques for adjusting aggressiveness of approximation.
ICCD
Tomoki Nakamura, Kazutaka Tomida, Shouta Kouno, Hidetsugu Irie, Shuichi Sakai
2021 J jnl
Toward Wirelessly Cooperated Shape-Changing Computing Particles.
IEEE Pervasive Comput.
Junichiro Kadomoto, Takuya Sasatani, Koya Narumi, Naoto Usami, Hidetsugu Irie, Shuichi Sakai, Yoshihiro Kawahara
2020 B conf
A High-Performance Out-of-Order Soft Processor Without Register Renaming.
FPL
Satoshi Mitsuno, Junichiro Kadomoto, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai
2020 — conf
A RISC-V Processor with an Inter-Chiplet Wireless Communication Interface for Shape-Changeable Computers.
COOL CHIPS
Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2020 — conf
A Self-Sensing Technique Using Inductively-Coupled Coils for Deformable User Interfaces.
AsianCHI@CHI
Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2020 — conf
An Inductively Coupled Wireless Bus for Chiplet-Based Systems.
ASP-DAC
Junichiro Kadomoto, Satoshi Mitsuno, Hidetsugu Irie, Shuichi Sakai
2020 C conf
Design of Shape-Changeable Chiplet-Based Computers Using an Inductively Coupled Wireless Bus Interface.
ICCD
Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2019 C conf
WiXI: An Inter-Chip Wireless Bus Interface for Shape-Changeable Chiplet-Based Computers.
ICCD
Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai
2018 — conf
An Area-Efficient Out-of-Order Soft-Core Processor Without Register Renaming.
FPT
Junichiro Kadomoto, Toru Koizumi, Akifumi Fukuda, Reoma Matsuo, Susumu Mashimo, Akifumi Fujita, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai
2018 J jnl
Bank-Aware Instruction Scheduler for a Multibanked Register File.
J. Inf. Process.
Junji Yamada, Ushio Jimbo, Ryota Shioya, Masahiro Goshima, Shuichi Sakai
2018 C conf
Estimating driver's readiness by understanding driving posture.
ICCE
Takahiro Yamada, Hidetsugu Irie, Masahiro Kunitake, Eiji Nagano, Shuichi Sakai
2018 — conf
Reduction of Instruction Increase Overhead by STRAIGHT Compiler.
CANDAR Workshops
Toru Koizumi, Satoshi Nakae, Akifumi Fukuda, Hidetsugu Irie, Shuichi Sakai
2018 A* conf
STRAIGHT: Hazardless Processor Architecture Without Register Renaming.
MICRO
Hidetsugu Irie, Toru Koizumi, Akifumi Fukuda, Seiya Akaki, Satoshi Nakae, Yutaro Bessho, Ryota Shioya, Takahiro Notsu, Katsuhiro Yoda, Teruo Ishihara, Shuichi Sakai
2017 C conf
Accelerating Integrity Verification on Secure Processors by Promissory Hash.
PRDC
Mizuki Miyanaga, Hidetsugu Irie, Shuichi Sakai
2017 J jnl
Design of a Register Cache System with an Open Source Process Design Kit for 45nm Technology.
IEICE Trans. Electron.
Junji Yamada, Ushio Jimbo, Ryota Shioya, Masahiro Goshima, Shuichi Sakai
2017 J jnl
Skewed Multistaged Multibanked Register File for Area and Energy Efficiency.
IEICE Trans. Inf. Syst.
Junji Yamada, Ushio Jimbo, Ryota Shioya, Masahiro Goshima, Shuichi Sakai
2016 C conf
"Stubborn" strategy to mitigate remaining cache misses.
ICCD
Hayato Nomura, Hiroyuki Katchi, Hidetsugu Irie, Shuichi Sakai
2016 J jnl
An Inductive Method to Select Simulation Points.
IEICE Trans. Inf. Syst.
Minseong Choi, Takashi Fukuda, Masahiro Goshima, Shuichi Sakai
2016 — conf
High-Accuracy Joint Position Estimation and Posture Detection System for Driving.
MobiQuitous (Adjunct Proceedings)
Takahiro Yamada, Hidetsugu Irie, Shuichi Sakai
2015 J jnl
Address Order Violation Detection with Parallel Counting Bloom Filters.
IEICE Trans. Electron.
Naruki Kurata, Ryota Shioya, Masahiro Goshima, Shuichi Sakai
2015 — conf
An Inductive Method to Select Simulation Points.
CANDAR
Minseong Choi, Takashi Fukuda, Masahiro Goshima, Shuichi Sakai
2014 — conf
A cloud architecture for protecting guest's information from malicious operators with memory management.
CODASPY
Koki Murakami, Tsuyoshi Yamada, Rie Shigetomi Yamaguchi, Masahiro Goshima, Shuichi Sakai
2013 J jnl
Register Indirect Jump Target Forwarding.
IEICE Trans. Inf. Syst.
Ryota Shioya, Naruki Kurata, Takashi Toyoshima, Masahiro Goshima, Shuichi Sakai
2011 J jnl
Low-Overhead Architecture for Security Tag.
IEICE Trans. Inf. Syst.
Ryota Shioya, Daewung Kim, Kazuo Horio, Masahiro Goshima, Shuichi Sakai
2010 A* conf
Register Cache System Not for Latency Reduction Purpose.
MICRO
Ryota Shioya, Kazuo Horio, Masahiro Goshima, Shuichi Sakai
2009 — conf
Dependable VLSI: device, design and architecture: how should they cooperate?
ASP-DAC
Shuichi Sakai, Hidetoshi Onodera, Hiroto Yasuura, James C. Hoe
2009 C conf
Low-Overhead Architecture for Security Tag.
PRDC
Ryota Shioya, Daewung Kim, Kazuo Horio, Masahiro Goshima, Shuichi Sakai
2009 C conf
String-Wise Information Flow Tracking against Script Injection Attacks.
PRDC
Kunbo Li, Ryota Shioya, Masahiro Goshima, Shuichi Sakai
2008 J jnl
Ultra Dependable Processor.
IEICE Trans. Electron.
Shuichi Sakai, Masahiro Goshima, Hidetsugu Irie
2007 J jnl
Musical part separation based on perceptual hierarchy.
Syst. Comput. Jpn.
Tomoyoshi Kinoshita, Ibuki Handa, Makoto Muto, Shuichi Sakai, Hidehiko Tanaka
2007 J jnl
Preventing timing errors on register writes: mechanisms of detections and recoveries.
SIGARCH Comput. Archit. News
Hidetsugu Irie, Ken Sugimoto, Masahiro Goshima, Shuichi Sakai
2007 A conf
Utilization of SECDED for soft error and variation-induced defect tolerance in caches.
DATE
Luong Dinh Hung, Hidetsugu Irie, Masahiro Goshima, Shuichi Sakai
2006 C conf
Base Address Recognition with Data Flow Tracking for Injection Attack Detection.
PRDC
Satoshi Katsunuma, Hiroyuki Kurita, Ryota Shioya, Kazuto Shimizu, Hidetsugu Irie, Masahiro Goshima, Shuichi Sakai
2006 J jnl
Bus Serialization for Reducing Power Consumption.
Inf. Media Technol.
Naoya Hatta, Niko Demus Barli, Chitaka Iwama, Luong Dinh Hung, Daisuke Tashiro, Shuichi Sakai, Hidehiko Tanaka
2006 J jnl
Dynamic Estimation of Task Level Parallelism with Operating System Support.
Inf. Media Technol.
Luong Dinh Hung, Shuichi Sakai
2006 C conf
SEVA: A Soft-Error- and Variation-Aware Cache Architecture.
PRDC
Luong Dinh Hung, Masahiro Goshima, Shuichi Sakai
2005 J jnl
Associating semantically structured cooking videos with their preparation steps.
Syst. Comput. Jpn.
Koichi Miura, Motomu Takano, Reiko Hamada, Ichiro Ide, Shuichi Sakai, Hidehiko Tanaka
2005 A* conf
Cooking navi: assistant for daily cooking in kitchen.
ACM Multimedia
Reiko Hamada, Jun Okabe, Ichiro Ide, Shin'ichi Satoh, Shuichi Sakai, Hidehiko Tanaka
2005 — conf
Dynamic Estimation of Task Level Parallelism with Operating System Support.
ISPAN
Luong Dinh Hung, Shuichi Sakai
2005 C conf
Mitigating Soft Errors in Highly Associative Cache with CAM-based Tag.
ICCD
Luong Dinh Hung, Masahiro Goshima, Shuichi Sakai
2004 — conf
Multimedia Integration for Cooking Video Indexing.
PCM (2)
Reiko Hamada, Koichi Miura, Ichiro Ide, Shin'ichi Satoh, Shuichi Sakai, Hidehiko Tanaka
2003 J jnl
A note on greedy algorithms for the maximum weighted independent set problem.
Discret. Appl. Math.
Shuichi Sakai, Mitsunori Togasaki, Koichi Yamazaki
2003 — conf
Associating Cooking Video Segments with Preparation Steps.
CIVR
Koichi Miura, Reiko Hamada, Ichiro Ide, Shuichi Sakai, Hidehiko Tanaka
2003 J jnl
Compilation of dictionaries for semantic attribute analysis of television news captions.
Syst. Comput. Jpn.
Ichiro Ide, Reiko Hamada, Shuichi Sakai, Hidehiko Tanaka
2003 — conf
Compiler-Assisted Thread Level Control Speculation.
Euro-Par
Hideyuki Miura, Luong Dinh Hung, Chitaka Iwama, Daisuke Tashiro, Niko Demus Barli, Shuichi Sakai, Hidehiko Tanaka
2003 Misc conf
Complexity Analysis of a Cache Controller for Speculative Multithreading Chip Multiprocessors.
HiPC
Yoshimitsu Yanagawa, Luong Dinh Hung, Chitaka Iwama, Niko Demus Barli, Shuichi Sakai, Hidehiko Tanaka
2002 — conf
An object detection method for describing soccer games from video.
ICME (1)
Okihisa Utsumi, Koichi Miura, Ichiro Ide, Shuichi Sakai, Hidehiko Tanaka
2002 — conf
CMP on SoC: Architect's View.
ISSS
Shuichi Sakai
2001 — conf
An attribute based news video indexing.
ACM Multimedia Workshops
Ichiro Ide, Reiko Hamada, Shuichi Sakai, Hidehiko Tanaka
2001 — conf
Improving Conditional Branch Prediction on Speculative Multithreading Architectures.
Euro-Par
Chitaka Iwama, Niko Demus Barli, Shuichi Sakai, Hidehiko Tanaka
2000 — conf
Associating cooking video with related textbook.
ACM Multimedia Workshops
Reiko Hamada, Ichiro Ide, Shuichi Sakai
2000 — conf
Scene identification in news video by character region segmentation.
ACM Multimedia Workshops
Ichiro Ide, Reiko Hamada, Shuichi Sakai, Hidehiko Tanaka
2000 — conf
Structural analysis of cooking preparation steps in Japanese.
IRAL
Reiko Hamada, Ichiro Ide, Shuichi Sakai, Hidehiko Tanaka
1999 A* conf
Associating video with related documents.
ACM Multimedia (2)
Reiko Hamada, Ichiro Ide, Shuichi Sakai, Hidehiko Tanaka
1999 A* conf
Integrated Manipulation: Context-Aware Manipulation of 2D Diagrams.
ACM Symposium on User Interface Software and Technology
Masaaki Honda, Takeo Igarashi, Hidehiko Tanaka, Shuichi Sakai
1999 — conf
Inter-procedural Analysis for Parallelization of Java Programs.
ACPC
Antonio Magnaghi, Shuichi Sakai, Hidehiko Tanaka
1999 — conf
Relating Graphical Features with Concept Classes for Automatic News Video Indexing.
Intelligent Information Integration
Ichiro Ide, Reiko Hamada, Shuichi Sakai, Hidehiko Tanaka
1997 — conf
Experience with Fine-Grain Communication in EM-X Multiprocessor for Parallel Sparse Matrix Computation.
IPPS
Mitsuhisa Sato, Yuetsu Kodama, Hirofumi Sakane, Hayato Yamana, Shuichi Sakai, Yoshinori Yamaguchi
1997 B conf
Fine-Grain Multithreading with the EM-X Multiprocessor.
SPAA
Andrew Sohn, Yuetsu Kodama, Jui Ku, Mitsuhisa Sato, Hirofumi Sakane, Hayato Yamana, Shuichi Sakai, Yoshinori Yamaguchi
1997 — conf
Parallel Execution of Radix Sort Program Using Fine-Grain Communication.
IEEE PACT
Yuetsu Kodama, Hirofumi Sakane, Hanpei Koike, Mitsuhisa Sato, Shuichi Sakai, Yoshinori Yamaguchi
1997 Misc conf
Virtual control channel and its application to the massively parallel computer RWC-1.
HiPC
Takashi Yokota, Hiroshi Matsuoka, Kazuaki Okamoto, Hideo Hirono, Shuichi Sakai
1996 — conf
Identifying the capability of overlapping computation with communication.
IEEE PACT
Andrew Sohn, Jui Ku, Yuetsu Kodama, Mitsuhisa Sato, Hirofumi Sakane, Hayato Yamana, Shuichi Sakai, Yoshinori Yamaguchi
1996 — conf
Multithread execution mechanisms on RICA-1 for massively parallel computation.
IEEE PACT
Kazuaki Okamoto, Shuichi Sakai, Hiroshi Matsuoka, Takashi Yokota, Hideo Hirono
1995 A conf
A Macrotask-level Unlimited Speculative Execution on Multiprocessors.
International Conference on Supercomputing
Hayato Yamana, Mitsuhisa Sato, Yuetsu Kodama, Hirofumi Sakane, Shuichi Sakai, Yoshinori Yamaguchi
1995 C conf
A prototype router for the massively parallel computer RWC-1.
ICCD
Takashi Yokota, Hiroshi Matsuoka, Kazuaki Okamoto, Hideo Hirono, Atsushi Hori, Shuichi Sakai
1995 J jnl
Reduced Interprocessor-Communication Architecture and its Implementation on EM-4.
Parallel Comput.
Shuichi Sakai, Yuetsu Kodama, Mitsuhisa Sato, Andrew Shaw, Hiroshi Matsuoka, Hideo Hirono, Kazuaki Okamoto, Takashi Yokota
1995 A* conf
The EM-X Parallel Computer: Architecture and Basic Performance.
ISCA
Yuetsu Kodama, Hirohumi Sakane, Mitsuhisa Sato, Hayato Yamana, Shuichi Sakai, Yoshinori Yamaguchi
1995 C conf
Time Space Sharing Scheduling and Architectural Support.
JSSPP
Atsushi Hori, Takashi Yokota, Yutaka Ishikawa, Shuichi Sakai, Hiroki Konaka, Munenori Maeda, Takashi Tomokiyo, Jörg Nolte, Hiroshi Matsuoka, Kazuaki Okamoto, Hideo Hirono
1994 — conf
EM-C: Programming with Explicit Parallelism and Locality for EM-4 Multiprocessor.
IFIP PACT
Mitsuhisa Sato, Yuetsu Kodama, Shuichi Sakai, Yoshinori Yamaguchi
1994 — conf
Experience with Executing Shared Memory Programs using Fine-Grain Communication and Multithreading in EM-4.
IPPS
Mitsuhisa Sato, Yuetsu Kodama, Yoshinori Yamaguchi, Shuichi Sakai
1994 — conf
Message-based efficient remote memory access on a highly parallel computer EM-X.
ISPAN
Yuetsu Kodama, Hirofumi Sakane, Mitsuhisa Sato, Shuichi Sakai, Yoshinori Yamaguchi
1994 A conf
Nonnumeric search results on the EM-4 distributed-memory multiprocessor.
SC
Andrew Sohn, Mitsuhisa Sato, Shuichi Sakai, Yuetsu Kodama, Yoshinori Yamaguchi
1994 A conf
Overview of RWC Massively Parallel Computer Project.
HPDC
Shuichi Sakai
1994 — conf
Parallel bidirectional heuristic search on the EM-4 multiprocessor.
SPDP
Andrew Sohn, Mitsuhisa Sato, Shuichi Sakai, Yuetsu Kodama, Yoshinori Yamaguchi
1994 — conf
Programming with Distributed Data Structure for EM-X Multiprocessor.
Theory and Practice of Parallel Programming
Mitsuhisa Sato, Yuetsu Kodama, Hirofumi Sakane, Yoshinori Yamaguchi, Shuichi Sakai
1993 J jnl
Design and Implementation of a Circular Omega Network in the EM-4.
Parallel Comput.
Shuichi Sakai, Yuetsu Kodama, Yoshinori Yamaguchi
1993 A conf
EMC-Y: Parallel Processing Element Optimizing Communication and Computation.
International Conference on Supercomputing
Yuetsu Kodama, Yasuhito Koumura, Mitsuhisa Sato, Hirohumi Sakane, Shuichi Sakai, Yoshinori Yamaguchi
1993 J jnl
Evaluation of parallel execution performance by highly parallel computer EM-4.
Syst. Comput. Jpn.
Yuetsu Kodama, Shuichi Sakai, Yoshinori Yamaguchi
1993 — conf
RICA: Reduced Interprocessor-Communication Architecture - Concept and Mechanisms.
SPDP
Shuichi Sakai, Hiroshi Matsuoka, Yuetsu Kodama, Mitsuhisa Sato, Andrew Shaw, Hideo Hirono, Kazuaki Okamoto, Takashi Yokota
1993 A conf
Super-Threading: Architectural and Software Mechanisms for Optimizing Parallel Computation.
International Conference on Supercomputing
Shuichi Sakai, Kazuaki Okamoto, Hiroshi Matsuoka, Hideo Hirono, Yuetsu Kodama, Mitsuhisa Sato
1992 A conf
A priority forwarding scheme for real-time multistage interconnection networks.
RTSS
Kenji Toda, Kenji Nishida, Shuichi Sakai, Toshio Shimada
1992 J jnl
A prototype of a highly parallel dataflow machine EM-4 and its preliminary evaluation.
Future Gener. Comput. Syst.
Yuetsu Kodama, Shuichi Sakai, Yoshinori Yamaguchi
1992 — conf
Evaluation of the EM-4 Highly Parallel Computer using a Game Tree Searching Problem.
FGCS
Yuetsu Kodama, Shuichi Sakai, Yoshinori Yamaguchi
1992 J jnl
Methodologies in development and testing of the dataflow machine EM-4.
Parallel Comput.
Kazuaki Okamoto, Yuetsu Kodama, Shuichi Sakai, Yoshinori Yamaguchi
1992 A* conf
Thread-based Programming for the EM-4 Hybrid Dataflow Machine.
ISCA
Mitsuhisa Sato, Yuetsu Kodama, Shuichi Sakai, Yoshinori Yamaguchi, Yasuhito Koumura
1991 — conf
Design and Implementation of a Versatile Interconnection Network in the EM-4.
ICPP (1)
Shuichi Sakai, Yuetsu Kodama, Yoshinori Yamaguchi
1991 A conf
Load balancing by function distribution on the EM-4 prototype.
SC
Yuetsu Kodama, Shuichi Sakai, Yoshinori Yamaguchi
1991 — conf
Parallel Multi-Context Architecture with High-Speed Synchronization Mechanism.
IPPS
Kenji Toda, Kenji Nishida, Yoshinobu Uchibori, Shuichi Sakai, Toshio Shimada
1991 — conf
Prototype Implementation of a Highly Parallel Dataflow Machine EM-4.
IPPS
Shuichi Sakai, Yuetsu Kodama, Yoshinori Yamaguchi
1990 A conf
Dataflow computer development in Japan.
ICS
Toshitsugu Yuba, Toshio Shimada, Yoshinori Yamaguchi, Kei Hiraki, Shuichi Sakai
1989 — conf
An Architectural Disgn of a Highly Parallel Dataflow Machine.
IFIP Congress
Yoshinori Yamaguchi, Shuichi Sakai, Kei Hiraki, Yuetsu Kodama
1989 A* conf
An Architecture of a Dataflow Single Chip Processor.
ISCA
Shuichi Sakai, Yoshinori Yamaguchi, Kei Hiraki, Yuetsu Kodama, Toshitsugu Yuba
1986 J jnl
Interconnection networks for bucket distribution on relational algebra machine GRACE.
Syst. Comput. Jpn.
Shuichi Sakai, Masaru Kitsuregawa, Hidehiko Tanaka, Tohru Moto-Oka
1985 J jnl
Interconnection network for bucket collection on relational algebra machine GRACE.
Syst. Comput. Jpn.
Shuichi Sakai, Masaru Kitsuregawa, Hidehiko Tanaka, Tohru Moto-Oka