Shuichi Ichikawa

45 papers A* 1A 1B 4C 1Misc 5Journal 21Unranked 12
YearRankTypeTitle / Venue / Authors
2025 J jnl
Performance Enhancement of the LFSR-Based Unpredictable Random Number Generator in Rocket Core.
IEICE Trans. Inf. Syst.
Takayoshi Shikano, Shuichi Ichikawa
2024 — conf
Random Number Generation Based on Cryptocurrency Prices and Linear Feedback Shift Register.
CANDAR
Ayumu Chiba, Shuichi Ichikawa
2023 J jnl
Design and Implementation of an On-Line Quality Control System for Latch-Based True Random Number Generator.
IEICE Trans. Inf. Syst.
Naoki Fujieda, Shuichi Ichikawa, Ryusei Oya, Hitomi Kishibe
2023 — conf
Pseudo-Random Number Generation by Staggered Sampling of LFSR.
candar
Shuichi Ichikawa
2022 — conf
An HLS implementation of on-the-fly randomness test for TRNGs.
CANDAR
Ryusei Oya, Naoki Fujieda, Shuichi Ichikawa
2021 J jnl
A true random number generator that utilizes thermal noise in a programmable system-on-chip (PSoC).
Int. J. Circuit Theory Appl.
Shunsuke Matsuoka, Shuichi Ichikawa, Naoki Fujieda
2020 J jnl
An Analysis of DCM-Based True Random Number Generator.
IEEE Trans. Circuits Syst. II Express Briefs
Naoki Fujieda, Masaaki Takeda, Shuichi Ichikawa
2020 — conf
Netlist-based Measures for Hardware Obfuscation: A Preliminary Study.
CANDAR (Workshops)
Shotaro Yamada, Shuichi Ichikawa
2019 B conf
A light-weight implementation of latch-based true random number generator.
IWCMC
Naoki Fujieda, Hitomi Kishibe, Shuichi Ichikawa
2018 C conf
A Multiple Clock Domain Design of High-radix Montgomery Multiplication for Simplicity.
TENCON
Naoki Fujieda, Yusuke Ayuzawa, Masato Hongo, Shuichi Ichikawa
2018 J jnl
A latch-latch composition of metastability-based true random number generator for Xilinx FPGAs.
IEICE Electron. Express
Naoki Fujieda, Shuichi Ichikawa
2018 — conf
An Analysis on Randomness of Path ORAM for Light-Weight Implementation.
CANDAR Workshops
Hiroki Fujita, Naoki Fujieda, Shuichi Ichikawa
2018 J jnl
Evaluation of Register Number Abstraction for Enhanced Instruction Register Files.
IEICE Trans. Inf. Syst.
Naoki Fujieda, Kiyohiro Sato, Ryodai Iwamoto, Shuichi Ichikawa
2017 — conf
A Study of a Fault-Tolerant System Using Dynamic Partial Reconfiguration.
CANDAR
Seiya Ogido, Chikatoshi Yamada, Kei Miyagi, Shuichi Ichikawa
2017 J jnl
A Virtual Cache for Overlapped Memory Accesses of Path ORAM.
Int. J. Netw. Comput.
Naoki Fujieda, Ryo Yamauchi, Hiroki Fujita, Shuichi Ichikawa
2017 — conf
An Obfuscated Hardwired Sequence Control System Generated by High Level Synthesis.
CANDAR
Yoshiki Ishigaki, Naoki Fujieda, Yuumi Matsuoka, Kazuki Uyama, Shuichi Ichikawa
2017 — conf
Evaluation of the hardwired sequence control system generated by high-level synthesis.
ISIE
Naoki Fujieda, Shuichi Ichikawa, Yoshiki Ishigaki, Tasuku Tanaka
2016 J jnl
Design and implementation of instruction indirection for embedded software obfuscation.
Microprocess. Microsystems
Naoki Fujieda, Tasuku Tanaka, Shuichi Ichikawa
2016 — conf
Last Path Caching: A Simple Way to Remove Redundant Memory Accesses of Path ORAM.
CANDAR
Naoki Fujieda, Ryo Yamauchi, Shuichi Ichikawa
2015 — conf
A Complement to Enhanced Instruction Register File against Embedded Software Falsification.
PPREW@ACSAC
Naoki Fujieda, Kiyohiro Sato, Shuichi Ichikawa
2013 — conf
An XOR-Based Approach to Merging Entries for Instruction Register Files.
CANDAR
Naoki Fujieda, Shuichi Ichikawa
2012 J jnl
FPGA Implementation of Metastability-Based True Random Number Generator.
IEICE Trans. Inf. Syst.
Hisashi Hata, Shuichi Ichikawa
2012 Misc conf
Implementation and Evaluation of Modular Multiplication Based on Coarsely Integrated Operand Scanning.
ICNC
Satoru Tamura, Chikatoshi Yamada, Shuichi Ichikawa
2012 Misc conf
Reduction of Power Consumption in Key-specific AES Circuits.
ICNC
Shunsuke Matsuoka, Shuichi Ichikawa
2011 J jnl
Foreword.
IEICE Trans. Inf. Syst.
Shuichi Ichikawa
2009 Misc conf
Estimating the Optimal Configuration of a Multi-Core Cluster: A Preliminary Study.
CISIS
Shuichi Ichikawa, Shoichiro Takagi
2009 J jnl
Optimizing process allocation of parallel programs for heterogeneous clusters.
Concurr. Comput. Pract. Exp.
Shuichi Ichikawa, Sho Takahashi, Yuu Kawai
2008 J jnl
Diversification of Processors Based on Redundancy in Instruction Set.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Shuichi Ichikawa, Takashi Sawada, Hisashi Hata
2006 J jnl
Design and Evaluation of Data-Dependent Hardware for AES Encryption Algorithm.
IEICE Trans. Inf. Syst.
Ryoichiro Atono, Shuichi Ichikawa
2006 J jnl
Redundancy in Instruction Sequences of Computer Programs.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Kazuhiro Hattanda, Shuichi Ichikawa
2005 J jnl
Design and Evaluation of Hardware Pseudo-Random Number Generator MT19937.
IEICE Trans. Inf. Syst.
Shiro Konuma, Shuichi Ichikawa
2005 J jnl
Optimizing the configuration of a heterogeneous cluster with multiprocessing and execution-time estimation.
Parallel Comput.
Yoshinori Kishimoto, Shuichi Ichikawa
2004 A conf
An Execution-Time Estimation Model for Heterogeneous Clusters.
IPDPS
Yoshinori Kishimoto, Shuichi Ichikawa
2004 J jnl
The Design and Evaluation of Data-Dependent Hardware for Subgraph Isomorphism Problem.
IEICE Trans. Inf. Syst.
Shoji Yamamoto, Shuichi Ichikawa, Hiroshi Yamamoto
2004 J jnl
The Evaluation of Davidson's Digital Signature Scheme.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Kazuhiro Hattanda, Shuichi Ichikawa
2003 B conf
Data Dependent Circuit Design: A Case Study.
FPL
Shoji Yamamoto, Shuichi Ichikawa, Hiroshi Yamamoto
2002 B conf
Data Dependent Circuit for Subgraph Isomorphism Problem.
FPL
Shuichi Ichikawa, Shoji Yamamoto
2002 Misc conf
Redundancy in 3D Polygon Models and Its Application to Digital Signature.
WSCG
Shuichi Ichikawa, H. Chiyama, K. Akabane
2000 B conf
Evaluation of Accelerator Designs for Subgraph Isomorphism Problem.
FPL
Shuichi Ichikawa, Hidemitsu Saito, Lerdtanaseangtham Udorn, Kouji Konishi
2000 Misc conf
Hardware Accelerator for Subgraph Isomorphism Problems.
FCCM
Shuichi Ichikawa, Lerdtanaseangtham Udorn, Kouji Konishi
1992 J jnl
Evaluation of range-checking addressing modes and the architecture of FLATS2.
Syst. Comput. Jpn.
Shuichi Ichikawa, Mitsuhisa Sato, Eiichi Goto
1991 J jnl
Pseudorandom Rounding for Truncated Multipliers.
IEEE Trans. Computers
Nobuaki Yoshida, Eiichi Goto, Shuichi Ichikawa
1990 — conf
Multiple instruction streams in a highly pipelined processor.
SPDP
Mitsuhisa Sato, Shuichi Ichikawa, Eiichi Goto
1989 J jnl
CPC (Cyclic Pipeline Computer) - An Architecture Suited for Josephson and Pipelined-Memory Machines.
IEEE Trans. Computers
Kentaro Shimizu, Eiichi Goto, Shuichi Ichikawa
1989 A* conf
Run-Time Checking in Lisp by Integrating Memory Addressing and Range Checking.
ISCA
Mitsuhisa Sato, Shuichi Ichikawa, Eiichi Goto