Shuguo Li - RankMe

55 papers B 4C 10Journal 32Unranked 9

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	Design an Efficient FPGA-Based Accelerator for Leveled BFV Homomorphic Encryption. IEEE Trans. Circuits Syst. II Express Briefs Liang Kong, Guojie Qin, Shuguo Li
2024	J	`jnl`	Hardware Acceleration and Implementation of Fully Homomorphic Encryption Over the Torus. IEEE Trans. Circuits Syst. I Regul. Pap. Tianqi Kong, Shuguo Li
2024	J	`jnl`	Split-Radix Based Compact Hardware Architecture for CRYSTALS-Kyber. IEEE Trans. Computers Wenbo Guo, Shuguo Li
2023	J	`jnl`	Highly-Efficient Hardware Architecture for CRYSTALS-Kyber With a Novel Conflict-Free Memory Access Pattern. IEEE Trans. Circuits Syst. I Regul. Pap. Wenbo Guo, Shuguo Li
2022	J	`jnl`	An Efficient Implementation of KYBER. IEEE Trans. Circuits Syst. II Express Briefs Wenbo Guo, Shuguo Li, Liang Kong
2022	J	`jnl`	Optimized Interpolation of Four-Term Karatsuba Multiplication and a Method of Avoiding Negative Multiplicands. IEEE Trans. Circuits Syst. I Regul. Pap. Zhen Gu, Shuguo Li
2021	J	`jnl`	A Compact Hardware Implementation of CCA-Secure Key Exchange Mechanism CRYSTALS-KYBER on FPGA. IACR Trans. Cryptogr. Hardw. Embed. Syst. Yufei Xing, Shuguo Li
2021	C	`conf`	A Multibit Left-Shift Modular Inverse Hardware Algorithm and its Implementation. ISCAS Jinpeng Lu, Shuguo Li
2021	C	`conf`	Area-Efficient Modular Reduction Structure and Memory Access Scheme for NTT. ISCAS Shuguo Li, Wenbo Guo
2021	J	`jnl`	Design and Analysis of Approximate 4-2 Compressors for High-Accuracy Multipliers. IEEE Trans. Very Large Scale Integr. Syst. Tianqi Kong, Shuguo Li
2021	J	`jnl`	Fast Binary Counters and Compressors Generated by Sorting Network. IEEE Trans. Very Large Scale Integr. Syst. Wenbo Guo, Shuguo Li
2021	J	`jnl`	High-Performance Constant-Time Discrete Gaussian Sampling. IEEE Trans. Computers Liang Kong, Shuguo Li, Ruirui Liu
2020	C	`conf`	A Binary Counter Based on Stacking and Sorting. ICCE Yating Du, Shuguo Li
2020	C	`conf`	A High-Throughput Hardware Implementation of SHA-256 Algorithm. ISCAS Yimeng Chen, Shuguo Li
2020	J	`jnl`	A Low-Latency and Low-Cost Montgomery Modular Multiplier Based on NLP Multiplication. IEEE Trans. Circuits Syst. II Express Briefs Jinnan Ding, Shuguo Li
2020	—	`conf`	A New Implementation of 16-bit Parallel Prefix Adder for High Speed and Low Area. ICDSP Qing Liao, Shuguo Li
2020	C	`conf`	A Novel Method of Modular Multiplication Based on Karatsuba-like Multiplication. ARITH Zhen Gu, Shuguo Li
2020	J	`jnl`	An Efficient Implementation of the NewHope Key Exchange on FPGAs. IEEE Trans. Circuits Syst. I Regul. Pap. Yufei Xing, Shuguo Li
2020	J	`jnl`	RLWE-Oriented High-Speed Polynomial Multiplier Utilizing Multi-Lane Stockham NTT Algorithm. IEEE Trans. Circuits Syst. II Express Briefs Xiang Feng, Shuguo Li, Sufen Xu
2019	C	`conf`	A Design and Implementation of Montgomery Modular Multiplier. ISCAS Ruirui Liu, Shuguo Li
2019	J	`jnl`	A Division-Free Toom-Cook Multiplication-Based Montgomery Modular Multiplication. IEEE Trans. Circuits Syst. II Express Briefs Zhen Gu, Shuguo Li
2019	J	`jnl`	A Generalized RNS Mclaughlin Modular Multiplication with Non-Coprime Moduli Sets. IEEE Trans. Computers Zhen Gu, Shuguo Li
2019	J	`jnl`	Accelerating an FHE Integer Multiplier Using Negative Wrapped Convolution and Ping-Pong FFT. IEEE Trans. Circuits Syst. II Express Briefs Xiang Feng, Shuguo Li
2019	J	`jnl`	High-Speed ECC Processor Over NIST Prime Fields Applied With Toom-Cook Multiplication. IEEE Trans. Circuits Syst. I Regul. Pap. Jinnan Ding, Shuguo Li, Zhen Gu
2018	J	`jnl`	A Modular Multiplier Implemented With Truncated Multiplication. IEEE Trans. Circuits Syst. II Express Briefs Jinnan Ding, Shuguo Li
2018	C	`conf`	An Implementation of Karatsuba-based Montgomery Modular Multiplication with Only Half-size Additions. ISCAS Zhen Gu, Shuguo Li
2018	J	`jnl`	High-Performance Pipelined Architecture of Point Multiplication on Koblitz Curves. IEEE Trans. Circuits Syst. II Express Briefs Lijuan Li, Shuguo Li
2018	J	`jnl`	Improved Algorithms and Implementations for Integer to τ NAF Conversion for Koblitz Curves. IEEE Trans. Circuits Syst. I Regul. Pap. Lijuan Li, Shuguo Li
2018	—	`conf`	Lazy Reduction and Multi-Precision Division Based on Modular Reductions. APCCAS Shuguo Li, Zhen Gu
2017	C	`conf`	A 3DES implementation especially for CBC feedback loop mode. ISCAS Yongcheng He, Shuguo Li
2017	—	`conf`	A High-Speed and SPA-Resistant Implementation of ECC Point Multiplication Over GF(p). TrustCom/BigDataSE/ICESS Xiang Feng, Shuguo Li
2017	—	`conf`	A Reconfigurable High-Speed ECC Processor Over NIST Primes. TrustCom/BigDataSE/ICESS Jinnan Ding, Shuguo Li
2017	—	`conf`	A design for high speed leading-zero counter. ISCE Jia Miao, Shuguo Li
2017	C	`conf`	A new digital true random number generator based on delay chain feedback loop. ISCAS Xufan Wu, Shuguo Li
2017	—	`conf`	Base Extent Optimization for RNS Montgomery Algorithm. TrustCom/BigDataSE/ICESS Yifeng Mo, Shuguo Li
2017	B	`conf`	Broken-Karatsuba multiplication and its application to Montgomery modular multiplication. FPL Jinnan Ding, Shuguo Li
2017	—	`conf`	Design of a fast number theoretical transform engine for fully homomorphic encryption. ISCE Xiang Feng, Shuguo Li
2017	J	`jnl`	Design of an Area-Effcient Million-Bit Integer Multiplier Using Double Modulus NTT. IEEE Trans. Very Large Scale Integr. Syst. Xiang Feng, Shuguo Li
2017	B	`conf`	Determine the carry bit of carry-sum generated by unsigned MBE multiplier without final addition. FPL Jinnan Ding, Shuguo Li
2017	B	`conf`	Fast RNS implementation of elliptic curve point multiplication in GF(p) with selected base pairs. FPL Yifeng Mo, Shuguo Li
2017	C	`conf`	Fast inversion in GF(2m) with polynomial basis using optimal addition chains. ISCAS Lijuan Li, Shuguo Li
2017	B	`conf`	High throughput AES encryption/decryption with efficient reordering and merging techniques. FPL Lijuan Li, Shuguo Li
2016	J	`jnl`	A High-Speed Digital True Random Number Generator Based on Cross Ring Oscillator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yuanhao Wang, Shuguo Li
2016	J	`jnl`	High-Performance Pipelined Architecture of Elliptic Curve Scalar Multiplication Over GF(2 IEEE Trans. Very Large Scale Integr. Syst. Lijuan Li, Shuguo Li
2016	J	`jnl`	The ASIC Implementation of SM3 Hash Algorithm for High Throughput. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Xiaojing Du, Shuguo Li
2015	J	`jnl`	A High Performance FPGA Implementation of 256-bit Elliptic Curve Cryptography Processor Over GF( IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Xiang Feng, Shuguo Li
2015	J	`jnl`	Fast RSA decryption through high-radix scalable Montgomery modular multipliers. Sci. China Inf. Sci. Tao Wu, Shuguo Li, Litian Liu
2014	J	`jnl`	A Digital TRNG Based on Cross Feedback Ring Oscillators. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Lijuan Li, Shuguo Li
2013	J	`jnl`	Fast, compact and symmetric modular exponentiation architecture by common-multiplicand Montgomery modular multiplications. Integr. Tao Wu, Shuguo Li, Litian Liu
2011	—	`conf`	CSA-based design of feedforward scalable montgomery modular multiplier. ISSPIT Tao Wu, Shuguo Li, Litian Liu
2010	J	`jnl`	Random numbers from an integrated CMOS double-scroll. IEICE Electron. Express Shuguo Li, Fuqiang Cao
2009	J	`jnl`	Area-delay efficient parallel architecture for Fermat number transform. IEICE Electron. Express Shuguo Li, Jian Zhang
2009	J	`jnl`	Data-recovery algorithm and circuit for cyclic convolution based on FNT. IEICE Electron. Express Jian Zhang, Shuguo Li
2009	J	`jnl`	Efficient FPGA implementation of sharp FIR filters using the FRM technique. IEICE Electron. Express Shuguo Li, Jian Zhang
2009	—	`conf`	High Speed Parallel Architecture for Cyclic Convolution Based on FNT. ISVLSI Jian Zhang, Shuguo Li