Shugang Wei - RankMe

28 papers C 2Misc 1Journal 11Unranked 14

Year	Rank	Type	Title / Venue / Authors
2020	J	`jnl`	Novel Binary Signed-Digit Addition Algorithm for FPGA Implementation. J. Circuits Syst. Comput. Yuuki Tanaka, Yuuki Suzuki, Shugang Wei
2016	—	`conf`	Computation of modular multiplicative inverses using residue signed-digit additions. ISOCC Shugang Wei
2015	—	`conf`	Fast signed-digit arithmetic circuits for residue number systems. ICECS Shugang Wei
2014	—	`conf`	Conversions between RNS and mixed-radix numbers using signed-digit arithmetic. ISIC Shugang Wei
2014	J	`jnl`	Efficient squaring circuit using canonical signed-digit number representation. IEICE Electron. Express Yuuki Tanaka, Shugang Wei
2013	J	`jnl`	High-Speed Modular Multipliers Based on a New Binary Signed-Digit Adder Tree Structure. J. Circuits Syst. Comput. Mingda Zhang, Shugang Wei
2013	J	`jnl`	RESIDUE-WEIGHTED NUMBER CONVERSION FOR MODULI SET {2 J. Circuits Syst. Comput. Changjun Jiang, Shugang Wei
2012	—	`conf`	An RSA encryption implementation method using residue signed-digit arithmetic circuits. BMEI Shugang Wei
2012	—	`conf`	Residue-weighted number conversion for moduli set {22 NEWCAS Changjun Jiang, Shugang Wei
2011	—	`conf`	Efficient residue checker using new binary modular adder tree structure for error detection of arithmetic. FSKD Mingda Zhang, Shugang Wei
2006	J	`jnl`	Modulo (2 J. Circuits Syst. Comput. Shugang Wei, Kensuke Shimizu
2006	J	`jnl`	New Booth Modulo Inf. Media Technol. Shuangching Chen, Shugang Wei
2006	J	`jnl`	Performance Evaluation of Signed-Digit Architecture for Weighted-to-Residue and Residue-to-Weighted Number Converters with Moduli Set (2 Inf. Media Technol. Shuangching Chen, Shugang Wei
2006	C	`conf`	Weighted-to-residue and residue-to-weighted converters with three-moduli (2 ISCAS Shuangching Chen, Shugang Wei
2005	J	`jnl`	Dynamic Range Compression Characteristics Using an Interpolating Polynomial for Digital Audio Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shugang Wei, Kensuke Shimizu
2005	—	`conf`	Number conversions between RNS and mixed-radix number system based on Modulo (2 SBCCI Shugang Wei
2003	—	`conf`	Modulo (2 ISCAS (5) Shugang Wei, Kensuke Shimizu
2003	J	`jnl`	Residue Checker with Signed-Digit Arithmetic for Error Detection of Arithmetic Circuits. J. Circuits Syst. Comput. Shugang Wei, Kensuke Shimizu
2002	—	`conf`	Fast modular multiplication using Booth recoding based on signed-digit number arithmetic. APCCAS (2) Shugang Wei, Shuangching Chen, Kensuke Shimizu
2002	—	`conf`	Residue signed-digit arithmetic circuit with a complement of modulus and the application to RSA encryption processor. ICECS Shugang Wei, Kensuke Shimizu
2001	—	`conf`	Error Detection of Arithmetic Circuits Using a Residue Checker with Signed-Digit Number System. DFT Shugang Wei, Kensuke Shimizu
2001	—	`conf`	Fast residue arithmetic multipliers based on signed-digit number system. ICECS Shugang Wei, Kensuke Shimizu
2000	C	`conf`	Residue arithmetic circuits using a signed-digit number representation. ISCAS Shugang Wei, Kensuke Shimizu
1999	—	`conf`	Residue Arithmetic Circuits Based on Signed-Digit Number Representation and the VHDL Implementation. Great Lakes Symposium on VLSI Shugang Wei, Kensuke Shimizu
1999	Misc	`conf`	Residue Arithmetic Multiplier Based on the Radix-4 Signed-Digit Multiple-Valued Arithmetic Circuits. VLSI Design Shugang Wei, Kensuke Shimizu
1998	—	`conf`	Residue Arithmetic Circuits Based on the Signed-Digit Multiple-Valued Arithmetic Circuits. ISMVL Shugang Wei, Kensuke Shimizu
1991	J	`jnl`	Performance evaluation of a multivalued rsa encryption vlsi. Syst. Comput. Jpn. Shugang Wei, Michitaka Kameyama, Tatsuo Higuchi
1990	J	`jnl`	Design of an RSA Encryption Processor Based on Signed-Digit Multivalued Arithmetic Circuits. Syst. Comput. Jpn. Michitaka Kameyama, Shugang Wei, Tatsuo Higuchi