Shuanglong Liu

39 papers A 5B 3C 1Misc 2Journal 12Unranked 15

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	DCP-CNN: Efficient Acceleration of CNNs With Dynamic Computing Parallelism on FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kui Dai, Zheren Xie, Shuanglong Liu
2025	J	`jnl`	Efficient CORDIC-Based Activation Functions for RNN Acceleration on FPGAs. IEEE Trans. Artif. Intell. Shen Wan, Junye Jiang, Minghan Li, Shuanglong Liu
2025	A	`conf`	FPGA-Based Acceleration of MCMC Algorithm through Self-Shrinking for Big Data. DATE Shuanglong Liu, Shiyu Peng, Wan Shen
2025	J	`jnl`	FPGA-based Acceleration for Convolutional Neural Networks: A Comprehensive Review. CoRR Junye Jiang, Yaan Zhou, Yuanhao Gong, Haoxuan Yuan, Shuanglong Liu
2024	J	`jnl`	Design of Fully Spectral CNNs for Efficient FPGA-Based Acceleration. IEEE Trans. Neural Networks Learn. Syst. Shuanglong Liu, Hongxiang Fan, Wayne Luk
2024	J	`jnl`	Enhancing Dropout-based Bayesian Neural Networks with Multi-Exit on FPGA. CoRR Hao Mark Chen, Liam Castelli, Martin Ferianc, Hongyu Zhou, Shuanglong Liu, Wayne Luk, Hongxiang Fan
2023	J	`jnl`	High-Performance Acceleration of 2-D and 3-D CNNs on FPGAs Using Static Block Floating Point. IEEE Trans. Neural Networks Learn. Syst. Hongxiang Fan, Shuanglong Liu, Zhiqiang Que, Xinyu Niu, Wayne Luk
2022	—	`conf`	Algorithm and Hardware Co-design for Reconfigurable CNN Accelerator. ASP-DAC Hongxiang Fan, Martin Ferianc, Zhiqiang Que, He Li, Shuanglong Liu, Xinyu Niu, Wayne Luk
2022	J	`jnl`	FPGA-Based Acceleration for Bayesian Convolutional Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hongxiang Fan, Martin Ferianc, Zhiqiang Que, Shuanglong Liu, Xinyu Niu, Miguel R. D. Rodrigues, Wayne Luk
2022	J	`jnl`	Toward Full-Stack Acceleration of Deep Convolutional Neural Networks on FPGAs. IEEE Trans. Neural Networks Learn. Syst. Shuanglong Liu, Hongxiang Fan, Martin Ferianc, Xinyu Niu, Huifeng Shi, Wayne Luk
2021	A	`conf`	Accelerating Fully Spectral CNNs with Adaptive Activation Functions on FPGA. DATE Shuanglong Liu, Hongxiang Fan, Wayne Luk
2021	J	`jnl`	Algorithm and Hardware Co-design for Reconfigurable CNN Accelerator. CoRR Hongxiang Fan, Martin Ferianc, Zhiqiang Que, He Li, Shuanglong Liu, Xinyu Niu, Wayne Luk
2021	A	`conf`	Reconfigurable Acceleration of Short Read Mapping with Biological Consideration. FPGA Ho-Cheung Ng, Izaak Coleman, Shuanglong Liu, Wayne Luk
2020	—	`conf`	Acceleration of Short Read Alignment with Runtime Reconfiguration. FPT Ho-Cheung Ng, Shuanglong Liu, Izaak Coleman, Ringo S. W. Chu, Man-Chung Yue, Wayne Luk
2020	C	`conf`	Optimizing FPGA-Based CNN Accelerator Using Differentiable Neural Architecture Search. ICCD Hongxiang Fan, Martin Ferianc, Shuanglong Liu, Zhiqiang Que, Xinyu Niu, Wayne Luk
2020	—	`conf`	Optimizing Fully Spectral Convolutional Neural Networks on FPGA. FPT Shuanglong Liu, Wayne Luk
2019	—	`conf`	Efficient Weight Reuse for Large LSTMs. ASAP Zhiqiang Que, Thomas Nugent, Shuanglong Liu, Li Tian, Xinyu Niu, Yongxin Zhu, Wayne Luk
2019	—	`conf`	F-E3D: FPGA-based Acceleration of an Efficient 3D Convolutional Neural Network for Human Action Recognition. ASAP Hongxiang Fan, Cheng Luo, Chenglong Zeng, Martin Ferianc, Zhiqiang Que, Shuanglong Liu, Xinyu Niu, Wayne Luk
2019	—	`conf`	Optimizing CNN-Based Hyperspectral Image Classification on FPGAs. ARC Shuanglong Liu, Ringo S. W. Chu, Xiwei Wang, Wayne Luk
2019	J	`jnl`	Optimizing CNN-based Hyperspectral ImageClassification on FPGAs. CoRR Shuanglong Liu, Ringo S. W. Chu, Xiwei Wang, Wayne Luk
2019	Misc	`conf`	Towards Efficient Deep Neural Network Training by FPGA-Based Batch-Level Parallelism. FCCM Cheng Luo, Man-Kit Sit, Hongxiang Fan, Shuanglong Liu, Wayne Luk, Ce Guo
2019	B	`conf`	Towards an Efficient Accelerator for DNN-Based Remote Sensing Image Segmentation on FPGAs. FPL Shuanglong Liu, Wayne Luk
2018	A	`conf`	A Low-Power Deconvolutional Accelerator for Convolutional Neural Network Based Segmentation on FPGA: Abstract Only. FPGA Shuanglong Liu, Xinyu Niu, Wayne Luk
2018	—	`conf`	A Real-Time Object Detection Accelerator with Compressed SSDLite on FPGA. FPT Hongxiang Fan, Shuanglong Liu, Martin Ferianc, Ho-Cheung Ng, Zhiqiang Que, Shen Liu, Xinyu Niu, Wayne Luk
2018	A	`conf`	ADAM: Automated Design Analysis and Merging for Speeding up FPGA Development. FPGA Ho-Cheung Ng, Shuanglong Liu, Wayne Luk
2018	—	`conf`	Hardware Compilation of Deep Neural Networks: An Overview. ASAP Ruizhe Zhao, Shuanglong Liu, Ho-Cheung Ng, Erwei Wang, James J. Davis, Xinyu Niu, Xiwei Wang, Huifeng Shi, George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
2018	—	`conf`	Memory-Efficient Architecture for Accelerating Generative Networks on FPGA. FPT Shuanglong Liu, Chenglong Zeng, Hongxiang Fan, Ho-Cheung Ng, Jiuxi Meng, Zhiqiang Que, Xinyu Niu, Wayne Luk
2018	J	`jnl`	Optimizing CNN-based Segmentation with Deeply Customized Convolutional and Deconvolutional Architectures on FPGA. ACM Trans. Reconfigurable Technol. Syst. Shuanglong Liu, Hongxiang Fan, Xinyu Niu, Ho-Cheung Ng, Yang Chu, Wayne Luk
2018	B	`conf`	Reconfigurable Acceleration of 3D-CNNs for Human Action Recognition with Block Floating-Point Representation. FPL Hongxiang Fan, Ho-Cheung Ng, Shuanglong Liu, Zhiqiang Que, Xinyu Niu, Wayne Luk
2017	—	`—`	Acceleration of MCMC-based algorithms using reconfigurable logic. Shuanglong Liu
2017	J	`jnl`	An Unbiased MCMC FPGA-Based Accelerator in the Land of Custom Precision Arithmetic. IEEE Trans. Computers Shuanglong Liu, Grigorios Mingas, Christos-Savvas Bouganis
2017	—	`conf`	CNN-LSTM Neural Network Model for Quantitative Strategy Analysis in Stock Markets. ICONIP (2) Shuanglong Liu, Chao Zhang, Jinwen Ma
2017	Misc	`conf`	Communication-Aware MCMC Method for Big Data Applications on FPGAs. FCCM Shuanglong Liu, Christos-Savvas Bouganis
2017	B	`conf`	Reconfigurable acceleration of genetic sequence alignment: A survey of two decades of efforts. FPL Ho-Cheung Ng, Shuanglong Liu, Wayne Luk
2016	—	`conf`	Stacked Auto-Encoders for Feature Extraction with Neural Networks. BIC-TA (1) Shuanglong Liu, Chao Zhang, Jinwen Ma
2016	—	`conf`	Stock Price Prediction Through the Mixture of Gaussian Processes via the Precise Hard-cut EM Algorithm. ICIC (3) Shuanglong Liu, Jinwen Ma
2015	—	`conf`	An exact MCMC accelerator under custom precision regimes. FPT Shuanglong Liu, Grigorios Mingas, Christos-Savvas Bouganis
2014	—	`conf`	Parallel resampling for particle filters on FPGAs. FPT Shuanglong Liu, Grigorios Mingas, Christos-Savvas Bouganis
2012	—	`conf`	Self-map building in wireless sensor network based on TDOA measurements. MFI Shuanglong Liu, Yuchao Tang, Chun Zhang, Shigang Yue