Shuai Wang

23 papers A 4Journal 9Unranked 10
YearRankTypeTitle / Venue / Authors
2017 J jnl
Word- and Partition-Level Write Variation Reduction for Improving Non-Volatile Cache Lifetime.
ACM Trans. Design Autom. Electr. Syst.
Shuai Wang, Guangshan Duan, Yupeng Li, Qianhao Dong
2016 J jnl
Low Power Aging-Aware On-Chip Memory Structure Design by Duty Cycle Balancing.
J. Circuits Syst. Comput.
Shuai Wang, Tao Jin, Chuanlei Zheng, Guangshan Duan
2015 J jnl
On the characterization and optimization of system-level vulnerability for instruction caches in embedded processors.
Microprocess. Microsystems
Shuai Wang, Guangshan Duan
2014 — conf
Characterizing soft error vulnerability of cache coherence protocols for chip-multiprocessors.
DFT
Chuanlei Zheng, Shuai Wang
2014 A conf
Exploiting narrow-width values for improving non-volatile cache lifetime.
DATE
Guangshan Duan, Shuai Wang
2013 — conf
Combating NBTI-induced aging in data caches.
ACM Great Lakes Symposium on VLSI
Shuai Wang, Guangshan Duan, Chuanlei Zheng, Tao Jin
2012 J jnl
Exploring branch target buffer access filtering for low-energy and high-performance microarchitectures.
IET Comput. Digit. Tech.
Shuai Wang, Jie S. Hu, Sotirios G. Ziavras
2012 — conf
Exploring hardware transaction processing for reliable computing in chip-multiprocessors against soft errors.
DFT
Chuanlei Zheng, Parijat Shukla, Shuai Wang, Jie S. Hu
2012 A conf
Low power aging-aware register file design by duty cycle balancing.
DATE
Shuai Wang, Tao Jin, Chuanlei Zheng, Guangshan Duan
2012 J jnl
Replicating Tag Entries for Reliability Enhancement in Cache Tag Arrays.
IEEE Trans. Very Large Scale Integr. Syst.
Shuai Wang, Jie S. Hu, Sotirios G. Ziavras
2011 — conf
Characterizing the L1 Data Cache's Vulnerability to Transient Errors in Chip-Multiprocessors.
ISVLSI
Li Tang, Shuai Wang, Jie S. Hu, Xiaobo Sharon Hu
2010 — conf
TRB: Tag Replication Buffer for Enhancing the Reliability of the Cache Tag Array.
ISVLSI
Shuai Wang, Jie S. Hu, Sotirios G. Ziavras
2009 A conf
Exploiting narrow-width values for thermal-aware register file designs.
DATE
Shuai Wang, Jie S. Hu, Sotirios G. Ziavras, Sung Woo Chung
2009 J jnl
On the Characterization and Optimization of On-Chip Cache Reliability against Soft Errors.
IEEE Trans. Computers
Shuai Wang, Jie S. Hu, Sotirios G. Ziavras
2009 J jnl
On the Exploitation of Narrow-Width Values for Improving Register File Reliability.
IEEE Trans. Very Large Scale Integr. Syst.
Jie S. Hu, Shuai Wang, Sotirios G. Ziavras
2008 J jnl
Asymmetrically banked value-aware register files for low-energy and high-performance.
Microprocess. Microsystems
Shuai Wang, Hongyan Yang, Jie S. Hu, Sotirios G. Ziavras
2008 — conf
BTB Access Filtering: A Low Energy and High Performance Design.
ISVLSI
Shuai Wang, Jie S. Hu, Sotirios G. Ziavras
2008 J jnl
Self-Adaptive Data Caches for Soft-Error Reliability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shuai Wang, Jie S. Hu, Sotirios G. Ziavras
2007 — conf
Asymmetrically Banked Value-Aware Register Files.
ISVLSI
Shuai Wang, Hongyan Yang, Jie S. Hu, Sotirios G. Ziavras
2007 — conf
Vector Processing Support for FPGA-Oriented High Performance Applications.
ISVLSI
Hongyan Yang, Shuai Wang, Sotirios G. Ziavras, Jie S. Hu
2006 A conf
In-Register Duplication: Exploiting Narrow-Width Value for Improving Register File Reliability.
DSN
Jie S. Hu, Shuai Wang, Sotirios G. Ziavras
2006 — conf
On the Characterization of Data Cache Vulnerability in High-Performance Embedded Microprocessors.
ICSAMOS
Shuai Wang, Jie S. Hu, Sotirios G. Ziavras
2005 — conf
Resource-Driven Optimizations for Transient-Fault Detecting SuperScalar Microarchitectures.
Asia-Pacific Computer Systems Architecture Conference
Jie S. Hu, Greg M. Link, Johnsy K. John, Shuai Wang, Sotirios G. Ziavras