Shu-Chun Yang

12 papers Journal 4Unranked 8
YearRankTypeTitle / Venue / Authors
2026 — conf
8.2 A 32Gb/s 12.35Tb/s/mm
ISSCC
Wei-Chih Chen, Mu-Shan Lin, Chien-Chun Tsai, Shenggao Li, Wei-Shuo Lin, Yu-Jie Huang, Nai-Chen Cheng, Yu-Chi Chen, Wen-Hung Huang, Chin-Hua Wen, Hsin-Hung Kuo, Han-Tzung Ke, Jie-Ren Huang, Chang-Yi Li, Sheng-Tsung Lai, Shu-Chun Yang, Kuan-Ting Chou, Pei-Chen Chiou, Tsung-Hsien Tsai, Yi-Ting Chen, Yen-Ming Chen, Kenny Cheng-Hsiang Hsieh
2025 — conf
36.1 A 32Gb/s 10.5Tb/s/mm 0.6pJ/b UCIe-Compliant Low-Latency Interface in 3nm Featuring Matched-Delay for Dynamic Clock Gating.
ISSCC
Mu-Shan Lin, Chien-Chun Tsai, Shenggao Li, Wei-Chih Chen, Wen-Hung Huang, Yu-Chi Chen, Yu-Jie Huang, Alan J. Drake, Chin-Hua Wen, Paul Ranucci, Hsin-Hung Kuo, Aidong Yin, Shu-Chun Yang, Farsheed Mahmoudi, Han-Tzung Ke, Chao-Chieh Li, Nai-Chen Cheng, Jimmy Wang, Kevin Lin, Harry Liao, Jie-Ren Huang, Meng-Hsuan Wu, Kenny Cheng-Hsiang Hsieh, Nicholas Amatruda, William Polanco, David King, Todd Basso, Anwar Kashem
2025 — conf
UCle-Compliant Chiplet Interconnect Design Leveraging Cutting-Edge Packaging Technologies.
CICC
Yu-Jie Huang, Mu-Shan Lin, Chien-Chun Tsai, Wei-Chih Chen, Hsin-Hung Kuo, Shu-Chun Yang, Shenggao Li
2024 — conf
A 0.296pJ/bit 17.9Tb/s/mm
VLSI Technology and Circuits
Mu-Shan Lin, Chien-Chun Tsai, Shenggao Li, Tze-Chiang Huang, Wen-Hung Huang, Kate Huang, Yu-Chi Chen, Alex Liu, Yu-Jie Huang, Jimmy Wang, Shu-Chun Yang, Nai-Chen Cheng, Chao-Chieh Li, Hsin-Hung Kuo, Wei-Chih Chen, Chin-Hua Wen, Kevin Lin, Po-Yi Huang, Kenny Cheng-Hsiang Hsieh, Frank Lee
2024 J jnl
Dog identification based on textural features and spatial relation of noseprint.
Pattern Recognit.
Yung-Kuan Chan, Chuen-Horng Lin, Ching-Lin Wang, Keng-Chang Tu, Shu-Chun Yang, Meng-Hsiun Tsai, Shyr-Shen Yu
2024 J jnl
Dog nose-print recognition based on the shape and spatial features of scales.
Expert Syst. Appl.
Yung-Kuan Chan, Chuen-Horng Lin, Yuan-Rong Ben, Ching-Lin Wang, Shu-Chun Yang, Meng-Hsiun Tsai, Shyr-Shen Yu
2020 J jnl
A 7-nm 4-GHz Arm¹-Core-Based CoWoS¹ Chiplet Design for High-Performance Computing.
IEEE J. Solid State Circuits
Mu-Shan Lin, Tze-Chiang Huang, Chien-Chun Tsai, King-Ho Tam, Kenny Cheng-Hsiang Hsieh, Ching-Fang Chen, Wen-Hung Huang, Chi-Wei Hu, Yu-Chi Chen, Sandeep Kumar Goel, Chin-Ming Fu, Stefan Rusu, Chao-Chieh Li, Sheng-Yao Yang, Mei Wong, Shu-Chun Yang, Frank Lee
2019 — conf
A 56Gb/s PAM-4 Receiver with Voltage Pre-Shift CTLE and 10-Tap DFE of Tap-1 Speculation in 7nm FinFET.
VLSI Circuits
Wei-Chih Chen, Shu-Chun Yang, Yu-Nan Shih, Wen-Hung Huang, Chien-Chun Tsai, Kenny Cheng-Hsiang Hsieh
2019 — conf
A 7nm 4GHz Arm
VLSI Circuits
Mu-Shan Lin, Tze-Chiang Huang, Chien-Chun Tsai, King-Ho Tam, Kenny Cheng-Hsiang Hsieh, Tom Chen, Wen-Hung Huang, Jack Hu, Yu-Chi Chen, Sandeep Kumar Goel, Chin-Ming Fu, Stefan Rusu, Chao-Chieh Li, Sheng-Yao Yang, Mei Wong, Shu-Chun Yang, Frank Lee
2016 — conf
A 16nm 256-bit wide 89.6GByte/s total bandwidth in-package interconnect with 0.3V swing and 0.062pJ/bit power in InFO package.
Hot Chips Symposium
Mu-Shan Lin, Chien-Chun Tsai, Kenny Cheng-Hsiang Hsieh, Wen-Hung Huang, Yu-Chi Chen, Shu-Chun Yang, Chin-Ming Fu, Hao-Jie Zhan, Jinn-Yeh Chien, Shao-Yu Li, Y.-H. Chen, C.-C. Kuo, Shih-Peng Tai, Kazuyoshi Yamada
2014 J jnl
A 1 Tbit/s Bandwidth 1024 b PLL/DLL-Less eDRAM PHY Using 0.3 V 0.105 mW/Gbps Low-Swing IO for CoWoS Application.
IEEE J. Solid State Circuits
Mu-Shan Lin, Chien-Chun Tsai, Chih-Hsien Chang, Wen-Hung Huang, Ying-Yu Hsu, Shu-Chun Yang, Chin-Ming Fu, Mao-Hsuan Chou, Tien-Chien Huang, Ching-Fang Chen, Tze-Chiang Huang, Saman Adham, Min-Jer Wang, William Wu Shen, Ashok Mehta
2010 — conf
A 2.5-8Gb/s transceiver with 5-tap DFE and Second order CDR against 28-inch channel and 5000ppm SSC in 40nm CMOS technology.
CICC
Wei-Chih Chen, Chien-Chun Tsai, Chih-Hsien Chang, Yung-Chow Peng, Fu-Lung Hsueh, Tsung-Hsin Yu, Jinn-Yeh Chien, Wen-Hung Huang, Chi-Chang Lu, Mu-Shan Lin, Chin-Ming Fu, Shu-Chun Yang, Chung-Wing Wong, Wan-Te Chen, Chin-Hua Wen, Li Yueh Wang, Chiang Pu