Shrutisagar Chandrasekaran

14 papers B 3C 1Journal 4Unranked 6
YearRankTypeTitle / Venue / Authors
2009 — conf
Efficient systolic architecture and power modeling for finite ridgelet transform.
ICCV Workshops
Abdul Naser Sazish, Shrutisagar Chandrasekaran, Abbes Amira
2008 J jnl
A segmentation concept for positron emission tomography imaging using multiresolution analysis.
Neurocomputing
Abbes Amira, Shrutisagar Chandrasekaran, David W. G. Montgomery, Isa Servan Uzun
2008 J jnl
An efficient VLSI architecture and FPGA implementation of the Finite Ridgelet Transform.
J. Real Time Image Process.
Shrutisagar Chandrasekaran, Abbes Amira, Minghua Shi, Amine Bermak
2008 J jnl
FPGA Realization of FIR Filters by Efficient and Flexible Systolization Using Distributed Arithmetic.
IEEE Trans. Signal Process.
Pramod Kumar Meher, Shrutisagar Chandrasekaran, Abbes Amira
2008 — conf
High Performance FPGA Implementation of the Mersenne Twister.
DELTA
Shrutisagar Chandrasekaran, Abbes Amira
2007 — conf
A New Behavioural Power Modelling Approach for FPGA based Custom Cores.
AHS
Shrutisagar Chandrasekaran, Abbes Amira
2007 C conf
Novel Sparse OBC based Distributed Arithmetic Architecture for Matrix Transforms.
ISCAS
Shrutisagar Chandrasekaran, Abbes Amira
2007 J jnl
Power Modeling and Efficient FPGA Implementation of FHT for Signal Processing.
IEEE Trans. Very Large Scale Integr. Syst.
Abbes Amira, Shrutisagar Chandrasekaran
2006 — conf
An Efficient FPGA Implementation of Gaussian Mixture Models-Based Classifier Using Distributed Arithmetic.
ICECS
Minghua Shi, Amine Bermak, Shrutisagar Chandrasekaran, Abbes Amira
2006 B conf
FPGA Implementation and Power Modelling of the Fast Walsh Transform.
FPL
Shrutisagar Chandrasekaran, Abbes Amira
2006 — conf
Power Modeling and Efficient FPGA Implementation of Color Space Conversion.
ICECS
Faycal Bensaali, Abbes Amira, Shrutisagar Chandrasekaran
2006 B conf
Power Reduction for FPGA Implementations : Design Optimisation and High Level Modelling.
FPL
Shrutisagar Chandrasekaran, Abbes Amira
2005 — conf
An area efficient low power inner product computation for discrete orthogonal transforms.
ICIP (3)
Shrutisagar Chandrasekaran, Abbes Amira
2005 B conf
High Speed / Low Power Architectures for the Finite Radon Transform.
FPL
Shrutisagar Chandrasekaran, Abbes Amira