Shrirang K. Karandikar

13 papers A* 2A 2Journal 5Unranked 4
YearRankTypeTitle / Venue / Authors
2012 — conf
FIRA - a novel method for benchmarking the cache hierarchy.
COMPUTE
Varad R. Deshmukh, Nishchay S. Mhatre, Shrirang K. Karandikar
2008 J jnl
Technology Mapping Using Logical Effort for Solving the Load-Distribution Problem.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shrirang K. Karandikar, Sachin S. Sapatnekar
2007 J jnl
Fast Algorithms for Slew-Constrained Minimum Cost Buffering.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Chin Ngai Sze
2007 — conf
Fast Electrical Correction Using Resizing and Buffering.
ASP-DAC
Shrirang K. Karandikar, Charles J. Alpert, Mehmet Can Yildiz, Paul Villarrubia, Stephen T. Quay, T. Mahmud
2007 J jnl
Techniques for Fast Physical Synthesis.
Proc. IEEE
Charles J. Alpert, Shrirang K. Karandikar, Zhuo Li, Gi-Joon Nam, Stephen T. Quay, Haoxing Ren, Cliff C. N. Sze, Paul G. Villarrubia, Mehmet Can Yildiz
2007 — conf
The nuts and bolts of physical synthesis.
SLIP
Charles J. Alpert, Shrirang K. Karandikar, Zhuo Li, Gi-Joon Nam, Stephen T. Quay, Haoxing Ren, Cliff C. N. Sze, Paul G. Villarrubia, Mehmet Can Yildiz
2006 A* conf
Fast algorithms for slew constrained minimum cost buffering.
DAC
Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Cliff C. N. Sze
2005 J jnl
Fast comparisons of circuit implementations.
IEEE Trans. Very Large Scale Integr. Syst.
Shrirang K. Karandikar, Sachin S. Sapatnekar
2005 — conf
Fast estimation of area-delay trade-offs in circuit sizing.
ISCAS (4)
Shrirang K. Karandikar, Sachin S. Sapatnekar
2004 A conf
Fast Comparisons of Circuit Implementations.
DATE
Shrirang K. Karandikar, Sachin S. Sapatnekar
2004 A conf
Logical effort based technology mapping.
ICCAD
Shrirang K. Karandikar, Sachin S. Sapatnekar
2003 J jnl
Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect.
IEEE Trans. Very Large Scale Integr. Syst.
Shrirang K. Karandikar, Sachin S. Sapatnekar
2001 A* conf
Technology Mapping for SOI Domino Logic Incorporating Solutions for the Parasitic Bipolar Effect.
DAC
Shrirang K. Karandikar, Sachin S. Sapatnekar