Shreesha Srinath

14 papers A* 8A 2Journal 2Unranked 2

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	From Pragmas to Partners: A Symbiotic Evolution of Agentic High-Level Synthesis. CoRR Niansong Zhang, Sunwoo Kim, Shreesha Srinath, Zhiru Zhang
2021	A*	`conf`	Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation. MICRO Nursultan Kabylkas, Tommy Thorn, Shreesha Srinath, Polychronis Xekalakis, Jose Renau
2018	A*	`conf`	A modular digital VLSI flow for high-productivity SoC design. DAC Brucek Khailany, Evgeni Khmer, Rangharajan Venkatesan, Jason Clemons, Joel S. Emer, Matthew Fojtik, Alicia Klinefelter, Michael Pellauer, Nathaniel Ross Pinckney, Yakun Sophia Shao, Shreesha Srinath, Christopher Torng, Sam Likun Xi, Yanqing Zhang, Brian Zimmer
2018	A*	`conf`	An Architectural Framework for Accelerating Dynamic Parallel Algorithms on Reconfigurable Hardware. MICRO Tao Chen, Shreesha Srinath, Christopher Batten, G. Edward Suh
2017	A	`conf`	Dynamic Hazard Resolution for Pipelining Irregular Loops in High-Level Synthesis. FPGA Steve Dai, Ritchie Zhao, Gai Liu, Shreesha Srinath, Udit Gupta, Christopher Batten, Zhiru Zhang
2017	A*	`conf`	Using intra-core loop-task accelerators to improve the productivity and performance of task-based parallel programs. MICRO Ji Kim, Shunning Jiang, Christopher Torng, Moyang Wang, Shreesha Srinath, Berkin Ilbeyi, Khalid Al-Hawaj, Christopher Batten
2016	—	`conf`	Experiences using a novel Python-based hardware modeling framework for computer architecture test chips. Hot Chips Symposium Christopher Torng, Moyang Wang, Bharath Sudheendra, Nagaraj Murali, Suren Jayasuriya, Shreesha Srinath, Taylor Pritchard, Robin Ying, Christopher Batten
2016	A*	`conf`	Improving high-level synthesis with decoupled data structure optimization. DAC Ritchie Zhao, Gai Liu, Shreesha Srinath, Christopher Batten, Zhiru Zhang
2014	A*	`conf`	Architectural Specialization for Inter-Iteration Loop Dependence Patterns. MICRO Shreesha Srinath, Berkin Ilbeyi, Mingxing Tan, Gai Liu, Zhiru Zhang, Christopher Batten
2013	J	`jnl`	Design and Implementation of an "Approximate" Communication System for Wireless Media Applications. IEEE/ACM Trans. Netw. Sayandeep Sen, Tan Zhang, Syed Gilani, Shreesha Srinath, Suman Banerjee, Sateesh Addepalli
2013	A*	`conf`	Microarchitectural mechanisms to exploit value structure in SIMT architectures. ISCA Ji Kim, Christopher Torng, Shreesha Srinath, Derek Lockhart, Christopher Batten
2010	A	`conf`	Automatic generation of high-performance multipliers for FPGAs with asymmetric multiplier blocks. FPGA Shreesha Srinath, Katherine Compton
2010	A*	`conf`	Design and implementation of an "approximate" communication system for wireless media applications. SIGCOMM Sayandeep Sen, Syed Gilani, Shreesha Srinath, Stephen Schmitt, Suman Banerjee
2008	—	`conf`	Rough Neuron Based Neural Classifier. ICETET Ashwin Kothari, Avinash G. Keskar, Rakesh Chalasani, Shreesha Srinath