Shouyi Yin - RankMe

403 papers A* 55A 21B 3C 27Misc 5Journal 199Unranked 93

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	2.9 A 0.24mJ/Frame Quadratic Interpolation 4DGS Processor with Recursive Computation Reuse and Tree-Based Parallel-Rendering. ISSCC Xiaolong Yang, Yang Wang, Wende Xu, Yubin Qin, Huanyu Wang, Ruiqi Guo, Zhiheng Yue, Jiangyuan Gu, Shaojun Wei, Yang Hu, Shouyi Yin
2026	—	`conf`	A 28nm 47.3TFLOPs/W 894mJ/Inference Visual Autoregressive Accelerator with Differential-Amplifier Speculation and Chain-Reaction-Like Parallel Generation. ISSCC Zhiheng Yue, Xujiang Xiang, Jiamu Fu, Shaojun Wei, Yang Wang, Yang Hu, Shouyi Yin
2026	—	`conf`	A 28nm Speculative-Decoding LLM Processor Achieving 105-to-685µs/Token Latency for Billion-Parameter Models. ISSCC Yang Wang, Huanyu Wang, Jiaxin Yang, Yutong Su, Ruiqi Guo, Zhiheng Yue, Jiangyuan Gu, Shaojun Wei, Yang Hu, Shouyi Yin
2026	J	`jnl`	A Hierarchical-Hybrid Floating-Point Compute-in-Memory Macro Using FP-DAC and FP-ADC for Edge-AI Devices. IEEE J. Solid State Circuits Yuanzhe Zhao, Yang Wang, Rui Paulo Martins, Chi-Hang Chan, Shouyi Yin, Minglei Zhang
2026	—	`conf`	BitStopper: An Efficient Transformer Attention Accelerator via Stage-fusion and Early Termination. ASP-DAC Huizheng Wang, Hongbin Wang, Shaojun Wei, Yang Hu, Shouyi Yin
2026	J	`jnl`	Designing Spatial Architectures for Sparse Attention: STAR Accelerator via Cross-Stage Tiling. IEEE Trans. Computers Huizheng Wang, Taiquan Wei, Hongbin Wang, Zichuan Wang, Xinru Tang, Zhiheng Yue, Shaojun Wei, Yang Hu, Shouyi Yin
2026	J	`jnl`	ETCIM: Error-Tolerant Digital CIM Processor With Redundancy-Free Hard Error Repair and Run-Time Soft Error Correction. IEEE J. Solid State Circuits Yiqi Wang, Zhen He, Chenggang Zhao, Zihan Wu, Mingyu Gao, Huiming Han, Shaojun Wei, Yang Hu, Fengbin Tu, Shouyi Yin
2026	A*	`conf`	FACE: Fully Overlapped PD Scheduling and Multi-Level Architecture Co-Exploration on Wafer. HPCA Zheng Xu, Dehao Kong, Jiaxin Liu, Dingcheng Jiang, Xu Dai, Jinyi Deng, Yang Hu, Shouyi Yin
2026	A*	`conf`	HR-DCIM: High-Reliability Floating-Point Digital CIM Architecture With Unified Low-Cost Iterative Error Correction. HPCA Zhen He, Yiqi Wang, Zhiheng Yue, Zihan Wu, Huiming Han, Shaojun Wei, Yang Hu, Fengbin Tu, Shouyi Yin
2026	—	`conf`	LAPA: Log-Domain Prediction-Driven Dynamic Sparsity Accelerator for Transformer Model. ASP-DAC Huizheng Wang, Hongbin Wang, Shaojun Wei, Yang Hu, Shouyi Yin
2026	J	`jnl`	MRCIM: A Many-Core Reconfigurable Computing-in-Memory Processor Combining CPU and Tensor Modes for NN Acceleration. IEEE Trans. Circuits Syst. I Regul. Pap. Zhen He, Yiqi Wang, Zihan Wu, Huiming Han, Shaojun Wei, Yang Hu, Chao Li, Fengbin Tu, Shouyi Yin
2026	—	`conf`	MoBiLE: Efficient Mixture-of-Experts Inference on Consumer GPU with Mixture of Big Little Experts. ASP-DAC Yushu Zhao, Yubin Qin, Yang Wang, Xiaolong Yang, Huiming Han, Shaojun Wei, Yang Hu, Shouyi Yin
2026	A*	`conf`	MoEntwine: Unleashing the Potential of Wafer-Scale Chips for Large-Scale Expert Parallel Inference. HPCA Xinru Tang, Jingxiang Hou, Dingcheng Jiang, Taiquan Wei, Jiaxin Liu, Jinyi Deng, Huizheng Wang, Qize Yang, Haoran Shang, Chao Li, Yang Hu, Shouyi Yin
2026	A*	`conf`	PADE: A Predictor-Free Sparse Attention Accelerator via Unified Execution and Stage Fusion. HPCA Huizheng Wang, Hongbin Wang, Zichuan Wang, Zhiheng Yue, Yang Wang, Chao Li, Yang Hu, Shouyi Yin
2026	A*	`conf`	ReThermal: Co-Design of Thermal-Aware Static and Dynamic Scheduling for LLM Training on Liquid-Cooled Wafer-Scale Chips. HPCA Chengran Li, Huizheng Wang, Jiaxin Liu, Jingyao Liu, Zhiheng Yue, Xia Li, Shenfei Jiang, Jinyi Deng, Yang Hu, Shouyi Yin
2026	A*	`conf`	TEMP: A Memory Efficient Physical-Aware Tensor Partition-Mapping Framework on Wafer-Scale Chips. HPCA Huizheng Wang, Taiquan Wei, Zichuan Wang, Dingcheng Jiang, Qize Yang, Jiaxin Liu, Jingxiang Hou, Chao Li, Jinyi Deng, Yang Hu, Shouyi Yin
2026	A*	`conf`	WATOS: Efficient LLM Training Strategies and Architecture Co-Exploration for Wafer-Scale Chip. HPCA Huizheng Wang, Zichuan Wang, Hongbin Wang, Jingxiang Hou, Taiquan Wei, Chao Li, Yang Hu, Shouyi Yin
2026	—	`conf`	XY-Serve: End-to-End Versatile Production Serving for Dynamic LLM Workloads. ASPLOS (1) Mingcong Song, Xinru Tang, Fengfan Hou, Jing Li, Wei Wei, Yipeng Ma, Runqiu Xiao, Hongjie Si, Dingcheng Jiang, Shouyi Yin, Yang Hu, Guoping Long
2025	—	`conf`	14.4 A 51.6TFLOPs/W Full-Datapath CIM Macro Approaching Sparsity Bound and < ISSCC Zhiheng Yue, Xujiang Xiang, Yang Wang, Ruiqi Guo, Huiming Han, Shaojun Wei, Yang Hu, Shouyi Yin
2025	—	`conf`	23.8 An 88.36TOPS/W Bit-Level-Weight-Compressed Large-Language-Model Accelerator with Cluster-Aligned INT-FP-GEMM and Bi-Dimensional Workflow Reformulation. ISSCC Yubin Qin, Yang Wang, Jiachen Wang, Zhiwei Lin, Yushu Zhao, Shaojun Wei, Yang Hu, Shouyi Yin
2025	A*	`conf`	3D-PATH: A Hierarchy LUT Processing-in-memory Accelerator with Thermal-aware Hybrid Bonding Integration. MICRO Zhiheng Yue, Yang Wang, Chao Li, Shaojun Wei, Yang Hu, Shouyi Yin
2025	J	`jnl`	A 28-nm 28.8-TOPS/W Attention-Based NN Processor With Correlative CIM Ring Architecture and Dataflow-Reshaped Digital-Assisted CIM Array. IEEE J. Solid State Circuits Ruiqi Guo, Zhiheng Yue, Yang Wang, Hao Li, Te Hu, Yabing Wang, Hao Sun, Jeng-Long Hsu, Yaojun Zhang, Bonan Yan, Leibo Liu, Ru Huang, Shaojun Wei, Shouyi Yin
2025	—	`conf`	A 28nm Value-Wise Hybrid-Domain Compute-in-Memory Macro with Heterogeneous Memory Fabric and Asynchronous Sparsity Manager. CICC Yuanzhe Zhao, Yang Wang, Yuheng Wang, Heng Xie, Yan Zhu, Rui Paulo Martins, Chi-Hang Chan, Shouyi Yin, Minglei Zhang
2025	J	`jnl`	A Chiplet Platform for Intelligent Radar/Sonar Leveraging Domain-Specific Reusable Active Interposer. IEEE Trans. Very Large Scale Integr. Syst. Yafei Liu, Dejian Li, Zheng Yang, Chaoqin Zhang, Yunlai Zhang, Xiangyu Li, Mingwei Cao, Shouyi Yin
2025	J	`jnl`	An Energy-Efficient POSIT Compute-in-Memory Macro for High-Accuracy AI Applications. IEEE J. Solid State Circuits Yang Wang, Xiaolong Yang, Yubin Qin, Zhiren Zhao, Ruiqi Guo, Zhiheng Yue, Huiming Han, Shaojun Wei, Yang Hu, Shouyi Yin
2025	—	`conf`	AnalogAI: A Generalized Accuracy Recovery Framework for DNNs under Analog Computing. AICAS Yinghao Li, Jiaqi Lv, Xueling Wang, Xu Dai, Xufeng He, Lei Wang, Yiran Zhang, Xin Si, Yang Hu, Shouyi Yin
2025	J	`jnl`	BETA: A Bit-Grained Transformer Attention Accelerator With Efficient Early Termination. IEEE Trans. Circuits Syst. II Express Briefs Huizheng Wang, Hongbin Wang, Zhiheng Yue, Jingyao Liu, Taiquan Wei, Shaojun Wei, Yang Hu, Shouyi Yin
2025	J	`jnl`	BeaCIM: A Digital Compute-in-Memory DNN Processor With Bi-Directional Exponent Alignment for FP8 Training. IEEE Trans. Circuits Syst. II Express Briefs Yang Zhou, Yang Wang, Wenxin Yin, Yazheng Jiang, Jingchuan Wei, Yubin Qin, Yang Hu, Shaojun Wei, Shouyi Yin
2025	J	`jnl`	BitStopper: An Efficient Transformer Attention Accelerator via Stage-fusion and Early Termination. CoRR Huizheng Wang, Hongbin Wang, Shaojun Wei, Yang Hu, Shouyi Yin
2025	J	`jnl`	CV-CIM: A Hybrid Domain Xor-Derived Similarity-Aware Computation-in-Memory Supporting Cost-Volume Construction. IEEE J. Solid State Circuits Zhiheng Yue, Yang Wang, Huizheng Wang, Ruiqi Guo, Fengbin Tu, Jianxun Yang, Shaojun Wei, Yang Hu, Shouyi Yin
2025	—	`conf`	Computing Efficiency Improvement for Multi-PEA CGRA with Built-in Control Design. CF Jiangyuan Gu, Xunbo Hu, Zidi Qin, Shaojun Wei, Shouyi Yin
2025	A*	`conf`	Cramming a Data Center into One Cabinet, a Co-Exploration of Computing and Hardware Architecture of Waferscale Chip. ISCA Xingmao Yu, Dingcheng Jiang, Jinyi Deng, Jingyao Liu, Chao Li, Shouyi Yin, Yang Hu
2025	—	`conf`	DIAG: A Refined Four-layer Agile Hardware Developing Flow for Generating Flexible Reconfigurable Architectures. ASP-DAC Haojia Hui, Jiangyuan Gu, Xunbo Hu, Shaojun Wei, Shouyi Yin
2025	J	`jnl`	Designing Spatial Architectures for Sparse Attention: STAR Accelerator via Cross-Stage Tiling. CoRR Huizheng Wang, Taiquan Wei, Hongbin Wang, Zichuan Wang, Xinru Tang, Zhiheng Yue, Shaojun Wei, Yang Hu, Shouyi Yin
2025	J	`jnl`	Dyn-Bitpool: A 28 nm 27 TOPS/W Two-Sided Sparse CIM Accelerator Featuring a Balanced Workload Scheme and High CIM Macro Utilization. IEEE Trans. Circuits Syst. I Regul. Pap. Xujiang Xiang, Zhiheng Yue, Xiaolong Zhang, Shaojun Wei, Yang Hu, Shouyi Yin
2025	A*	`conf`	ER-DCIM: Error-Resilient Digital CIM Architecture with Run-Time MAC-Cell Error Correction. HPCA Zhen He, Yiqi Wang, Zihan Wu, Shaojun Wei, Yang Hu, Fengbin Tu, Shouyi Yin
2025	J	`jnl`	From Quarter to All: Accelerating Speculative LLM Decoding via Floating-Point Exponent Remapping and Parameter Sharing. CoRR Yushu Zhao, Yubin Qin, Yang Wang, Xiaolong Yang, Huiming Han, Shaojun Wei, Yang Hu, Shouyi Yin
2025	C	`conf`	GPE: A High-Performance Edge GNN Inference Processor with Multi-Parallelism Format-Variation Mechanism. ISCAS Zhou Wang, Haochen Du, Jiuren Zhou, Zhou Shu, Yanqing Xu, Vivek Mohan, Baoyi Han, Xiaonan Tang, Shushan Qiao, Shouyi Yin, Anil A. Bharath, Emmanuel M. Drakakis
2025	A*	`conf`	GPS: GNN-Based Two-Stage Pre-Scheduling Loop Mapping Method on CGRAs. DAC Mingyang Kou, Weiqing Ji, Shouyi Yin, Hailong Yao
2025	J	`jnl`	HPCTransCompile: An AI Compiler Generated Dataset for High-Performance CUDA Transpilation and LLM Preliminary Exploration. CoRR Jiaqi Lv, Xufeng He, Yanchen Liu, Xu Dai, Yang Hu, Shouyi Yin
2025	J	`jnl`	LAPA: Log-Domain Prediction-Driven Dynamic Sparsity Accelerator for Transformer Model. CoRR Huizheng Wang, Hongbin Wang, Shaojun Wei, Yang Hu, Shouyi Yin
2025	A*	`conf`	MCBP: A Memory-Compute Efficient LLM Inference Accelerator Leveraging Bit-Slice-enabled Sparsity and Repetitiveness. MICRO Huizheng Wang, Zichuan Wang, Zhiheng Yue, Yousheng Long, Taiquan Wei, Jianxun Yang, Yang Wang, Chao Li, Shaojun Wei, Yang Hu, Shouyi Yin
2025	J	`jnl`	MCBP: A Memory-Compute Efficient LLM Inference Accelerator Leveraging Bit-Slice-enabled Sparsity and Repetitiveness. CoRR Huizheng Wang, Zichuan Wang, Zhiheng Yue, Yousheng Long, Taiquan Wei, Jianxun Yang, Yang Wang, Chao Li, Shaojun Wei, Yang Hu, Shouyi Yin
2025	J	`jnl`	MoBiLE: Efficient Mixture-of-Experts Inference on Consumer GPU with Mixture of Big Little Experts. CoRR Yushu Zhao, Yubin Qin, Yang Wang, Xiaolong Yang, Huiming Han, Shaojun Wei, Yang Hu, Shouyi Yin
2025	J	`jnl`	MoEntwine: Unleashing the Potential of Wafer-scale Chips for Large-scale Expert Parallel Inference. CoRR Xinru Tang, Jingxiang Hou, Dingcheng Jiang, Taiquan Wei, Jiaxin Liu, Jinyi Deng, Huizheng Wang, Qize Yang, Haoran Shang, Chao Li, Yang Hu, Shouyi Yin
2025	A	`conf`	P2P-Chiplet: Partition and Placement Co-Optimization for Multi-Chiplet Architecture. ICCAD Qidie Wu, Jiangyuan Gu, Xuguang Yuan, Shaojun Wei, Shouyi Yin
2025	J	`jnl`	PADE: A Predictor-Free Sparse Attention Accelerator via Unified Execution and Stage Fusion. CoRR Huizheng Wang, Hongbin Wang, Zichuan Wang, Zhiheng Yue, Yang Wang, Chao Li, Yang Hu, Shouyi Yin
2025	—	`conf`	PAMA: Large-Scale GNN Acceleration with Pre-Aggregation in Multi-Node Architecture. ASAP Weiwei Wu, Fengbin Tu, Shaojun Wei, Xiangyu Li, Yang Hu, Shouyi Yin
2025	A*	`conf`	PD Constraint-aware Physical/Logical Topology Co-Design for Network on Wafer. ISCA Qize Yang, Taiquan Wei, Sihan Guan, Chengran Li, Haoran Shang, Jinyi Deng, Huizheng Wang, Chao Li, Lei Wang, Yan Zhang, Shouyi Yin, Yang Hu
2025	C	`conf`	RAM-Wafer: RL-Based Automatic Mapping Framework for Large-Scale AI Training on Wafer-Scale Computing. ICCD Xu Dai, Dehao Kong, Xufeng He, Zijun Xu, Shaopeng Zhai, Yang Hu, Shouyi Yin
2025	—	`conf`	RSPE: A High Energy Efficient SNN Inference Processor with RISC-V based Dynamic Pruning Mechanism. AICAS Zhou Wang, Haochen Du, Zhou Shu, Vivek Mohan, Liyuan Guo, Wei Mao, Baoyi Han, Xiaonan Tang, Shushan Qiao, Shouyi Yin, Anil A. Bharath, Manos Mic Drakakis
2025	J	`jnl`	Rethinking Control Flow in Spatial Architectures: Insights Into Control Flow Plane Design. IEEE Trans. Computers Jinyi Deng, Xinru Tang, Jiahao Zhang, Yuxuan Li, Linyun Zhang, Fengbin Tu, Shaojun Wei, Yang Hu, Shouyi Yin
2025	C	`conf`	STPE: An Energy-Efficient Edge-Device Transformer Inference Processor with Multi-Mode Data-Compression Scheme. ISCAS Zhou Wang, Haochen Du, Vivek Mohan, Jiuren Zhou, Zhou Shu, Yanqing Xu, Baoyi Han, Xiaonan Tang, Shushan Qiao, Shouyi Yin, Anil A. Bharath, Emmanuel M. Drakakis
2025	—	`conf`	Segmentation-Aware Optimization of Collective for Waferscale Chips. APPT Qize Yang, Jiaxin Liu, Taiquan Wei, Yuxin Jin, Shouyi Yin, Yang Hu
2025	—	`conf`	Spatial-Aware Orchestration of LLM Attention on Waferscale Chips. APPT Taiquan Wei, Huizheng Wang, Zichuan Wang, Shouyi Yin, Yang Hu
2025	J	`jnl`	TEMP: A Memory Efficient Physical-aware Tensor Partition-Mapping Framework on Wafer-scale Chips. CoRR Huizheng Wang, Taiquan Wei, Zichuan Wang, Dingcheng Jiang, Qize Yang, Jiaxin Liu, Jingxiang Hou, Chao Li, Jinyi Deng, Yang Hu, Shouyi Yin
2025	J	`jnl`	TensorCIM: Digital Computing-in-Memory Tensor Processor With Multichip-Module-Based Architecture for Beyond-NN Acceleration. IEEE J. Solid State Circuits Yiqi Wang, Zihan Wu, Weiwei Wu, Leibo Liu, Yang Hu, Shaojun Wei, Fengbin Tu, Shouyi Yin
2025	—	`conf`	UPE: A Device-Edge DNN Inference Artificial Intelligence Processor with Supporting Reconfigurable Training. AICAS Zhou Wang, Haochen Du, Yanqing Xu, Zhou Shu, Jiuren Zhou, Liyuan Guo, Baoyi Han, Xiaonan Tang, Shushan Qiao, Shouyi Yin, Anil A. Bharath, Manos Mic Drakakis
2025	A*	`conf`	WSC-LLM: Efficient LLM Service and Architecture Co-exploration for Wafer-scale Chips. ISCA Zheng Xu, Dehao Kong, Jiaxin Liu, Jinxi Li, Jingxiang Hou, Xu Dai, Chao Li, Shaojun Wei, Yang Hu, Shouyi Yin
2025	J	`jnl`	cuPilot: A Strategy-Coordinated Multi-agent Framework for CUDA Kernel Evolution. CoRR Jinwu Chen, Qidie Wu, Bin Li, Lin Ma, Xin Si, Yang Hu, Shouyi Yin, Jun Yang
2024	—	`conf`	15.1 A 0.795fJ/bit Physically-Unclonable Function-Protected TCAM for a Software-Defined Networking Switch. ISSCC Zhiheng Yue, Xujiang Xiang, Fengbin Tu, Yang Wang, Yiming Wang, Shaojun Wei, Yang Hu, Shouyi Yin
2024	—	`conf`	20.2 A 28nm 74.34TFLOPS/W BF16 Heterogenous CIM-Based Accelerator Exploiting Denoising-Similarity for Diffusion Models. ISSCC Ruiqi Guo, Lei Wang, Xiaofeng Chen, Hao Sun, Zhiheng Yue, Yubin Qin, Huiming Han, Yang Wang, Fengbin Tu, Shaojun Wei, Yang Hu, Shouyi Yin
2024	—	`conf`	34.1 A 28nm 83.23TFLOPS/W POSIT-Based Compute-in-Memory Macro for High-Accuracy AI Applications. ISSCC Yang Wang, Xiaolong Yang, Yubin Qin, Zhiren Zhao, Ruiqi Guo, Zhiheng Yue, Huiming Han, Shaojun Wei, Yang Hu, Shouyi Yin
2024	—	`conf`	A 22nm 54.94TFLOPS/W Transformer Fine-Tuning Processor with Exponent-Stationary Re-Computing, Aggressive Linear Fitting, and Logarithmic Domain Multiplicating. VLSI Technology and Circuits Yang Wang, Xiaolong Yang, Yubin Qin, Zhiren Zhao, Ruiqi Guo, Zhiheng Yue, Huiming Han, Shaojun Wei, Yang Hu, Shouyi Yin
2024	—	`conf`	A 28nm 118.26TOPS/W Multi-Dimensional Fault-Tolerant Al Processor Enabling Voltage-Frequency Scaling Below Point-of-First-Failure. A-SSCC Yang Wang, Xiaolong Yang, Yubin Qin, Zhiren Zhao, Ruiqi Guo, Zhiheng Yue, Shaojun Wei, Yang Hu, Shouyi Yin
2024	—	`conf`	A 28nm 314.6TLFOPS/W Reconfigurable Floating-Point Analog Compute-In-Memory Macro with Exponent Approximation and Two-Stage Sharing TD-ADC. CICC Pengyu He, Yuanzhe Zhao, Heng Xie, Yang Wang, Shouyi Yin, Li Li, Yan Zhu, Rui Paulo Martins, Chi-Hang Chan, Minglei Zhang
2024	—	`conf`	A 28nm 4170-TFLOPS/W/b and 195-TFLOPS/mm VLSI Technology and Circuits Ruiqi Guo, Xiaofeng Chen, Lei Wang, Fengbin Tu, Shaojun Wei, Yang Hu, Shouyi Yin
2024	—	`conf`	A 52.01 TFLOPS/W Diffusion Model Processor with Inter-Time-Step Convolution-Attention-Redundancy Elimination and Bipolar Floating-Point Multiplication. VLSI Technology and Circuits Yubin Qin, Yang Wang, Xiaolong Yang, Zhiren Zhao, Shaojun Wei, Yang Hu, Shouyi Yin
2024	—	`conf`	A Lightweight 3D D2D Interface for Active Interposer Chiplet Systems. ICTA Zheng Yang, Yafei Liu, Xiangyu Li, Shouyi Yin
2024	J	`jnl`	Ayaka: A Versatile Transformer Accelerator With Low-Rank Estimation and Heterogeneous Dataflow. IEEE J. Solid State Circuits Yubin Qin, Yang Wang, Dazheng Deng, Xiaolong Yang, Zhiren Zhao, Yang Zhou, Yuanqi Fan, Jingchuan Wei, Tianbao Chen, Leibo Liu, Shaojun Wei, Yang Hu, Shouyi Yin
2024	A*	`conf`	CAP: A General Purpose Computation-in-memory with Content Addressable Processing Paradigm. DAC Zhiheng Yue, Shaojun Wei, Yang Hu, Shouyi Yin
2024	J	`jnl`	CIMFormer: A Systolic CIM-Array-Based Transformer Accelerator With Token-Pruning-Aware Attention Reformulating and Principal Possibility Gathering. IEEE J. Solid State Circuits Ruiqi Guo, Xiaofeng Chen, Lei Wang, Yang Wang, Hao Sun, Jingchuan Wei, Huiming Han, Leibo Liu, Shaojun Wei, Yang Hu, Shouyi Yin
2024	A*	`conf`	Dyn-Bitpool: A Two-sided Sparse CIM Accelerator Featuring a Balanced Workload Scheme and High CIM Macro Utilization. DAC Xujiang Xiang, Zhiheng Yue, Yuxuan Li, Liuxin Lv, Shaojun Wei, Yang Hu, Shouyi Yin
2024	A*	`conf`	E2EMap: End-to-End Reinforcement Learning for CGRA Compilation via Reverse Mapping. HPCA Dajiang Liu, Yuxin Xia, Jiaxing Shang, Jiang Zhong, Peng Ouyang, Shouyi Yin
2024	—	`conf`	ETCIM: An Error-Tolerant Digital-CIM Processor with Redundancy-Free Repair and Run-Time MAC and Cell Error Correction. VLSI Technology and Circuits Yiqi Wang, Zhen He, Chenggang Zhao, Zihan Wu, Mingyu Gao, Huiming Han, Shaojun Wei, Yang Hu, Fengbin Tu, Shouyi Yin
2024	J	`jnl`	Efficient Orchestrated AI Workflows Execution on Scale-Out Spatial Architecture. IEEE Trans. Circuits Syst. Artif. Intell. Jinyi Deng, Xinru Tang, Zhiheng Yue, Guangyang Lu, Qize Yang, Jiahao Zhang, Jinxi Li, Chao Li, Shaojun Wei, Yang Hu, Shouyi Yin
2024	J	`jnl`	Efficient Orchestrated AI Workflows Execution on Scale-out Spatial Architecture. CoRR Jinyi Deng, Xinru Tang, Zhiheng Yue, Guangyang Lu, Qize Yang, Jiahao Zhang, Jinxi Li, Chao Li, Shaojun Wei, Yang Hu, Shouyi Yin
2024	A*	`conf`	Exploiting Similarity Opportunities of Emerging Vision AI Models on Hybrid Bonding Architecture. ISCA Zhiheng Yue, Huizheng Wang, Jiahao Fang, Jinyi Deng, Guangyang Lu, Fengbin Tu, Ruiqi Guo, Yuxuan Li, Yubin Qin, Yang Wang, Chao Li, Huiming Han, Shaojun Wei, Yang Hu, Shouyi Yin
2024	A*	`conf`	FQP: A Fibonacci Quantization Processor with Multiplication-Free Computing and Topological-Order Routing. DAC Xiaolong Yang, Yang Wang, Yubin Qin, Jiachen Wang, Shaojun Wei, Yang Hu, Shouyi Yin
2024	—	`conf`	GRS: A General RISC-V SIMD Vector Acceleration Processor for Artificial Intelligence Applications. APCCAS Zhou Wang, Haochen Du, Jiuren Zhou, Yang Zhou, Xiaonan Tang, Tianchun Ye, Shaojun Wei, Shushan Qiao, Shouyi Yin
2024	A*	`conf`	GSPO: A Graph Substitution and Parallelization Joint Optimization Framework for DNN Inference. DAC Zheng Xu, Xu Dai, Shaojun Wei, Shouyi Yin, Yang Hu
2024	A*	`conf`	MECLA: Memory-Compute-Efficient LLM Accelerator with Scaling Sub-matrix Partition. ISCA Yubin Qin, Yang Wang, Zhiren Zhao, Xiaolong Yang, Yang Zhou, Shaojun Wei, Yang Hu, Shouyi Yin
2024	J	`jnl`	MulTCIM: Digital Computing-in-Memory-Based Multimodal Transformer Accelerator With Attention-Token-Bit Hybrid Sparsity. IEEE J. Solid State Circuits Fengbin Tu, Zihan Wu, Yiqi Wang, Weiwei Wu, Leibo Liu, Yang Hu, Shaojun Wei, Shouyi Yin
2024	J	`jnl`	PALM: A Efficient Performance Simulator for Tiled Accelerators with Large-scale Model Training. CoRR Jiahao Fang, Huizheng Wang, Qize Yang, Dehao Kong, Xu Dai, Jinyi Deng, Yang Hu, Shouyi Yin
2024	A*	`conf`	PMP: Pattern Morphing-based Memory Partitioning in High-Level Synthesis. DAC Dajiang Liu, Decai Pan, Xiao Xiong, Jiaxing Shang, Shouyi Yin
2024	—	`conf`	RCPE: An Excellent Performance Training Processor with RISC-V based Compression Mechanism. AICAS Zhou Wang, Haochen Du, Baoyi Han, Yanqing Xu, Xiaonan Tang, Yang Zhou, Zhe Zheng, Wenpeng Cui, Yanwei Xiong, Shaojun Wei, Shushan Qiao, Shouyi Yin
2024	—	`conf`	RTPE: A High Energy Efficiency Inference Processor with RISC-V based Transformation Mechanism. AICAS Zhou Wang, Haochen Du, Baoyi Han, Yanqing Xu, Xiaonan Tang, Yang Zhou, Zhe Zheng, Wenpeng Cui, Yanwei Xiong, Shaojun Wei, Shushan Qiao, Shouyi Yin
2024	J	`jnl`	Review of chiplet-based design: system architecture and interconnection. Sci. China Inf. Sci. Yafei Liu, Xiangyu Li, Shouyi Yin
2024	A*	`conf`	SOFA: A Compute-Memory Optimized Sparsity Accelerator via Cross-Stage Coordinated Tiling. MICRO Huizheng Wang, Jiahao Fang, Xinru Tang, Zhiheng Yue, Jinxi Li, Yubin Qin, Sihan Guan, Qinze Yang, Yang Wang, Chao Li, Yang Hu, Shouyi Yin
2024	J	`jnl`	SOFA: A Compute-Memory Optimized Sparsity Accelerator via Cross-Stage Coordinated Tiling. CoRR Huizheng Wang, Jiahao Fang, Xinru Tang, Zhiheng Yue, Jinxi Li, Yubin Qin, Sihan Guan, Qize Yang, Yang Wang, Chao Li, Yang Hu, Shouyi Yin
2024	—	`conf`	SSPE: A Device-edge SNN Inference Artificial Intelligence Processor in Supporting Smart Computing. APCCAS Zhou Wang, Haochen Du, Jiuren Zhou, Yanqing Xu, Xiaonan Tang, Tianchun Ye, Shaojun Wei, Shushan Qiao, Shouyi Yin
2024	J	`jnl`	SWG: an architecture for sparse weight gradient computation. Sci. China Inf. Sci. Weiwei Wu, Fengbin Tu, Xiangyu Li, Shaojun Wei, Shouyi Yin
2024	J	`jnl`	Tackling the Dynamicity in a Production LLM Serving System with SOTA Optimizations via Hybrid Prefill/Decode/Verify Scheduling on Efficient Meta-kernels. CoRR Mingcong Song, Xinru Tang, Fengfan Hou, Jing Li, Wei Wei, Yipeng Ma, Runqiu Xiao, Hongjie Si, Dingcheng Jiang, Shouyi Yin, Yang Hu, Guoping Long
2023	—	`conf`	A 28nm 49.7TOPS/W Sparse Transformer Processor with Random-Projection-Based Speculation, Multi-Stationary Dataflow, and Redundant Partial Product Elimination. A-SSCC Yubin Qin, Yang Wang, Dazheng Deng, Xiaolong Yang, Zhiren Zhao, Yang Zhou, Yuanqi Fan, Jingchuan Wei, Tianbao Chen, Leibo Liu, Shaojun Wei, Yang Hu, Shouyi Yin
2023	—	`conf`	A 28nm 77.35TOPS/W Similar Vectors Traceable Transformer Processor with Principal-Component-Prior Speculating and Dynamic Bit-wise Stationary Computing. VLSI Technology and Circuits Yang Wang, Yubin Qin, Dazheng Deng, Xiaolong Yang, Zhiren Zhao, Ruiqi Guo, Zhiheng Yue, Leibo Liu, Shaojun Wei, Yang Hu, Shouyi Yin
2023	—	`conf`	A Systolic Computing-in-Memory Array based Accelerator with Predictive Early Activation for Spatiotemporal Convolutions. AICAS Xiaofeng Chen, Ruiqi Guo, Zhiheng Yue, Yang Hu, Leibo Liu, Shaojun Wei, Shouyi Yin
2023	J	`jnl`	An Energy-Efficient Transformer Processor Exploiting Dynamic Weak Relevances in Global Attention. IEEE J. Solid State Circuits Yang Wang, Yubin Qin, Dazheng Deng, Jingchuan Wei, Yang Zhou, Yuanqi Fan, Tianbao Chen, Hao Sun, Leibo Liu, Shaojun Wei, Shouyi Yin
2023	—	`conf`	CIMFormer: A 38.9TOPS/W-8b Systolic CIM-Array Based Transformer Processor with Token-Slimmed Attention Reformulating and Principal Possibility Gathering. A-SSCC Ruiqi Guo, Yang Wang, Xiaofeng Chen, Lei Wang, Hao Sun, Jingchuan Wei, Leibo Liu, Shaojun Wei, Yang Hu, Shouyi Yin
2023	A*	`conf`	CPE: An Energy-Efficient Edge-Device Training with Multi-dimensional Compression Mechanism. DAC Zhou Wang, Jingchuan Wei, Boxiao Han, Hongjun He, Leibo Liu, Shaojun Wei, Shouyi Yin
2023	—	`conf`	CV-CIM: A 28nm XOR-Derived Similarity-Aware Computation-in-Memory for Cost-Volume Construction. ISSCC Zhiheng Yue, Yang Wang, Huizheng Wang, Yabing Wang, Ruiqi Guo, Limei Tang, Leibo Liu, Shaojun Wei, Yang Hu, Shouyi Yin
2023	J	`jnl`	Catch-Up Distillation: You Only Need to Train Once for Accelerating Sampling. CoRR Shitong Shao, Xu Dai, Shouyi Yin, Lujun Li, Huanran Chen, Yang Hu
2023	A*	`conf`	DARIC: A Data Reuse-Friendly CGRA for Parallel Data Access via Elastic FIFOs. DAC Dajiang Liu, Di Mou, Rong Zhu, Yan Zhuang, Jiaxing Shang, Jiang Zhong, Shouyi Yin
2023	A*	`conf`	FACT: FFN-Attention Co-optimized Transformer Architecture with Eager Correlation Prediction. ISCA Yubin Qin, Yang Wang, Dazheng Deng, Zhiren Zhao, Xiaolong Yang, Leibo Liu, Shaojun Wei, Yang Hu, Shouyi Yin
2023	J	`jnl`	M2STaR: A Multimode Spatio-Temporal Redundancy Design for Fault-Tolerant Coarse-Grained Reconfigurable Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xiangyu Kong, Jianfeng Zhu, Xingchen Man, Guihuan Song, Yi Huang, Chenchen Deng, Pengfei Gou, Shouyi Yin, Shaojun Wei, Leibo Liu
2023	—	`conf`	MuITCIM: A 28nm $2.24 \mu\mathrm{J}$/Token Attention-Token-Bit Hybrid Sparse Digital CIM-Based Accelerator for Multimodal Transformers. ISSCC Fengbin Tu, Zihan Wu, Yiqi Wang, Weiwei Wu, Leibo Liu, Yang Hu, Shaojun Wei, Shouyi Yin
2023	A*	`conf`	RMP-MEM: A HW/SW Reconfigurable Multi-Port Memory Architecture for Multi-PEA Oriented CGRA. DAC Qidie Wu, Jiangyuan Gu, Youxu Lin, Boxiao Han, Hongjun He, Yang Hu, Leibo Liu, Shaojun Wei, Shouyi Yin
2023	J	`jnl`	ReDCIM: Reconfigurable Digital Computing- In -Memory Processor With Unified FP/INT Pipeline for Cloud AI Acceleration. IEEE J. Solid State Circuits Fengbin Tu, Yiqi Wang, Zihan Wu, Ling Liang, Yufei Ding, Bongjin Kim, Leibo Liu, Shaojun Wei, Yuan Xie, Shouyi Yin
2023	J	`jnl`	RePQC: A 3.4-uJ/Op 48-kOPS Post-Quantum Crypto-Processor for Multiple-Mathematical Problems. IEEE J. Solid State Circuits Yihong Zhu, Wenping Zhu, Chongyang Li, Min Zhu, Chenchen Deng, Chen Chen, Shuying Yin, Shouyi Yin, Shaojun Wei, Leibo Liu
2023	J	`jnl`	Reconfigurability, Why It Matters in AI Tasks Processing: A Survey of Reconfigurable AI Chips. IEEE Trans. Circuits Syst. I Regul. Pap. Shaojun Wei, Xinhan Lin, Fengbin Tu, Yang Wang, Leibo Liu, Shouyi Yin
2023	J	`jnl`	SDP: Co-Designing Algorithm, Dataflow, and Architecture for In-SRAM Sparse NN Acceleration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Fengbin Tu, Yiqi Wang, Ling Liang, Yufei Ding, Leibo Liu, Shaojun Wei, Shouyi Yin, Yuan Xie
2023	J	`jnl`	SPCIM: Sparsity-Balanced Practical CIM Accelerator With Optimized Spatial-Temporal Multi-Macro Utilization. IEEE Trans. Circuits Syst. I Regul. Pap. Yiqi Wang, Fengbin Tu, Leibo Liu, Shaojun Wei, Yuan Xie, Shouyi Yin
2023	J	`jnl`	STAR: An STGCN ARchitecture for Skeleton-Based Human Action Recognition. IEEE Trans. Circuits Syst. I Regul. Pap. Weiwei Wu, Fengbin Tu, Mengqi Niu, Zhiheng Yue, Leibo Liu, Shaojun Wei, Xiangyu Li, Yang Hu, Shouyi Yin
2023	J	`jnl`	TAEM 2.0: A Faster Transfer-Aware Effective Loop Mapping for Heterogeneous Resources on CGRA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mingyang Kou, Jiangyuan Gu, Hailong Yao, Shaojun Wei, Shouyi Yin
2023	—	`conf`	TPE: A High-Performance Edge-Device Inference with Multi-level Transformational Mechanism. AICAS Zhou Wang, Jingchuan Wei, Xiaonan Tang, Boxiao Han, Hongjun He, Leibo Liu, Shaojun Wei, Shouyi Yin
2023	J	`jnl`	TT@CIM: A Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity Optimization and Variable Precision Quantization. IEEE J. Solid State Circuits Ruiqi Guo, Zhiheng Yue, Xin Si, Hao Li, Te Hu, Limei Tang, Yabing Wang, Hao Sun, Leibo Liu, Meng-Fan Chang, Qiang Li, Shaojun Wei, Shouyi Yin
2023	—	`conf`	TensorCIM: A 28nm 3.7nJ/Gather and 8.3TFLOPS/W FP32 Digital-CIM Tensor Processor for MCM-CIM-Based Beyond-NN Acceleration. ISSCC Fengbin Tu, Yiqi Wang, Zihan Wu, Weiwei Wu, Leibo Liu, Yang Hu, Shaojun Wei, Shouyi Yin
2023	A*	`conf`	Towards Efficient Control Flow Handling in Spatial Architecture via Architecting the Control Flow Plane. MICRO Jinyi Deng, Xinru Tang, Jiahao Zhang, Yuxuan Li, Linyun Zhang, Boxiao Han, Hongjun He, Fengbin Tu, Leibo Liu, Shaojun Wei, Yang Hu, Shouyi Yin
2023	J	`jnl`	Towards Efficient Control Flow Handling in Spatial Architecture via Architecting the Control Flow Plane. CoRR Jinyi Deng, Xinru Tang, Jiahao Zhang, Yuxuan Li, Linyun Zhang, Fengbin Tu, Leibo Liu, Shaojun Wei, Yang Hu, Shouyi Yin
2023	J	`jnl`	TranCIM: Full-Digital Bitline-Transpose CIM-based Sparse Transformer Accelerator With Pipeline/Parallel Reconfigurable Modes. IEEE J. Solid State Circuits Fengbin Tu, Zihan Wu, Yiqi Wang, Ling Liang, Liu Liu, Yufei Ding, Leibo Liu, Shaojun Wei, Yuan Xie, Shouyi Yin
2023	J	`jnl`	Wafer-scale Computing: Advancements, Challenges, and Future Perspectives. CoRR Yang Hu, Xinhan Lin, Huizheng Wang, Zhen He, Xingmao Yu, Jiahao Zhang, Qize Yang, Zheng Xu, Sihan Guan, Jiahao Fang, Haoran Shang, Xinru Tang, Xu Dai, Shaojun Wei, Shouyi Yin
2023	J	`jnl`	WindMill: A Parameterized and Pluggable CGRA Implemented by DIAG Design Flow. CoRR Haojia Hui, Jiangyuan Gu, Xunbo Hu, Yang Hu, Leibo Liu, Shaojun Wei, Shouyi Yin
2022	J	`jnl`	A 12.1 TOPS/W Quantized Network Acceleration Processor With Effective-Weight-Based Convolution and Error-Compensation-Based Prediction. IEEE J. Solid State Circuits Huiyu Mo, Wenping Zhu, Wenjing Hu, Qiang Li, Ang Li, Shouyi Yin, Shaojun Wei, Leibo Liu
2022	—	`conf`	A 28nm 15.59µJ/Token Full-Digital Bitline-Transpose CIM-Based Sparse Transformer Accelerator with Pipeline/Parallel Reconfigurable Modes. ISSCC Fengbin Tu, Zihan Wu, Yiqi Wang, Ling Liang, Liu Liu, Yufei Ding, Leibo Liu, Shaojun Wei, Yuan Xie, Shouyi Yin
2022	—	`conf`	A 28nm 27.5TOPS/W Approximate-Computing-Based Transformer Processor with Asymptotic Sparsity Speculating and Out-of-Order Computing. ISSCC Yang Wang, Yubin Qin, Dazheng Deng, Jingchuan Wei, Yang Zhou, Yuanqi Fan, Tianbao Chen, Hao Sun, Leibo Liu, Shaojun Wei, Shouyi Yin
2022	—	`conf`	A 28nm 29.2TFLOPS/W BF16 and 36.5TOPS/W INT8 Reconfigurable Digital CIM Processor with Unified FP/INT Pipeline and Bitwise In-Memory Booth Multiplication for Cloud Deep Learning Acceleration. ISSCC Fengbin Tu, Yiqi Wang, Zihan Wu, Ling Liang, Yufei Ding, Bongjin Kim, Leibo Liu, Shaojun Wei, Yuan Xie, Shouyi Yin
2022	—	`conf`	A 28nm 48KOPS 3.4µJ/Op Agile Crypto-Processor for Post-Quantum Cryptography on Multi-Mathematical Problems. ISSCC Yihong Zhu, Wenping Zhu, Min Zhu, Chongyang Li, Chenchen Deng, Chen Chen, Shuying Yin, Shouyi Yin, Shaojun Wei, Leibo Liu
2022	J	`jnl`	A Compact and High-Performance Hardware Architecture for CRYSTALS-Dilithium. IACR Trans. Cryptogr. Hardw. Embed. Syst. Cankun Zhao, Neng Zhang, Hanning Wang, Bohan Yang, Wenping Zhu, Zhengdong Li, Min Zhu, Shouyi Yin, Shaojun Wei, Leibo Liu
2022	—	`conf`	A SHA-512 Hardware Implementation Based on Block RAM Storage Structure. IPDPS Workshops Mingyuan Yang, Yemeng Zhang, Bohan Yang, Hanning Wang, Shouyi Yin, Shaojun Wei, Leibo Liu
2022	J	`jnl`	An Energy-Efficient Approximate Divider Based on Logarithmic Conversion and Piecewise Constant Approximation. IEEE Trans. Circuits Syst. I Regul. Pap. Yong Wu, Honglan Jiang, Zining Ma, Pengfei Gou, Yong Lu, Jie Han, Shouyi Yin, Shaojun Wei, Leibo Liu
2022	J	`jnl`	An energy-efficient dynamically reconfigurable cryptographic engine with improved power/EM-side-channel-attack resistance. Sci. China Inf. Sci. Chenchen Deng, Min Zhu, Jinjiang Yang, Youyu Wu, Jiaji He, Bohan Yang, Jianfeng Zhu, Shouyi Yin, Shaojun Wei, Leibo Liu
2022	A*	`conf`	Atomic Dataflow based Graph-Level Workload Orchestration for Scalable DNN Accelerators. HPCA Shixuan Zheng, Xianjue Zhang, Leibo Liu, Shaojun Wei, Shouyi Yin
2022	J	`jnl`	BR-CIM: An Efficient Binary Representation Computation-In-Memory Design. IEEE Trans. Circuits Syst. I Regul. Pap. Zhiheng Yue, Yabing Wang, Yubin Qin, Leibo Liu, Shaojun Wei, Shouyi Yin
2022	J	`jnl`	BitCluster: Fine-Grained Weight Quantization for Load-Balanced Bit-Serial Neural Network Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ang Li, Huiyu Mo, Wenping Zhu, Qiang Li, Shouyi Yin, Shaojun Wei, Leibo Liu
2022	J	`jnl`	CFNTT: Scalable Radix-2/4 NTT Multiplication Architecture with an Efficient Conflict-free Memory Mapping Scheme. IACR Trans. Cryptogr. Hardw. Embed. Syst. Xiangren Chen, Bohan Yang, Shouyi Yin, Shaojun Wei, Leibo Liu
2022	A*	`conf`	CaSMap: agile mapper for reconfigurable spatial architectures by automatically clustering intermediate representations and scattering mapping process. ISCA Xingchen Man, Jianfeng Zhu, Guihuan Song, Shouyi Yin, Shaojun Wei, Leibo Liu
2022	J	`jnl`	Dynamic-II Pipeline: Compiling Loops With Irregular Branches on Static-Scheduling CGRA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Baofen Yuan, Jianfeng Zhu, Xingchen Man, Zijiao Ma, Shouyi Yin, Shaojun Wei, Leibo Liu
2022	J	`jnl`	Efficient FHE Radix-2 Arithmetic Operations Based on Redundant Encoding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zongsheng Hou, Neng Zhang, Bohan Yang, Hanning Wang, Min Zhu, Shouyi Yin, Shaojun Wei, Leibo Liu
2022	A*	`conf`	Efficient access scheme for multi-bank based NTT architecture through conflict graph. DAC Xiangren Chen, Bohan Yang, Yong Lu, Shouyi Yin, Shaojun Wei, Leibo Liu
2022	J	`jnl`	FAQS: Communication-efficient Federate DNN Architecture and Quantization Co-Search for personalized Hardware-aware Preferences. CoRR Hongjiang Chen, Yang Wang, Leibo Liu, Shaojun Wei, Shouyi Yin
2022	J	`jnl`	GQNA: Generic Quantized DNN Accelerator With Weight-Repetition-Aware Activation Aggregating. IEEE Trans. Circuits Syst. I Regul. Pap. Jianxun Yang, Fengbin Tu, Yixuan Li, Yiqi Wang, Leibo Liu, Shaojun Wei, Shouyi Yin
2022	J	`jnl`	Guest Editorial Introduction to the Special Section on the 2021 Asian Solid-State Circuits Conference (A-SSCC). IEEE J. Solid State Circuits Jung-Hwan Choi, Po-Chiun Huang, Shouyi Yin, Woogeun Rhee
2022	J	`jnl`	HQNAS: Auto CNN deployment framework for joint quantization and architecture search. CoRR Hongjiang Chen, Yang Wang, Leibo Liu, Shaojun Wei, Shouyi Yin
2022	A*	`conf`	MC-CIM: a reconfigurable computation-in-memory for efficient stereo matching cost computation. DAC Zhiheng Yue, Yabing Wang, Leibo Liu, Shaojun Wei, Shouyi Yin
2022	A*	`conf`	Mixed-granularity parallel coarse-grained reconfigurable architecture. DAC Jinyi Deng, Linyun Zhang, Lei Wang, Jiawei Liu, Kexiang Deng, Shibin Tang, Jiangyuan Gu, Boxiao Han, Fei Xu, Leibo Liu, Shaojun Wei, Shouyi Yin
2022	J	`jnl`	PL-NPU: An Energy-Efficient Edge-Device DNN Training Processor With Posit-Based Logarithm-Domain Computing. IEEE Trans. Circuits Syst. I Regul. Pap. Yang Wang, Dazheng Deng, Leibo Liu, Shaojun Wei, Shouyi Yin
2022	J	`jnl`	SWPU: A 126.04 TFLOPS/W Edge-Device Sparse DNN Training Processor With Dynamic Sub-Structured Weight Pruning. IEEE Trans. Circuits Syst. I Regul. Pap. Yang Wang, Yubin Qin, Leibo Liu, Shaojun Wei, Shouyi Yin
2022	J	`jnl`	Trainer: An Energy-Efficient Edge-Device Training Processor Supporting Dynamic Weight Pruning. IEEE J. Solid State Circuits Yang Wang, Yubin Qin, Dazheng Deng, Jingchuan Wei, Tianbao Chen, Xinhan Lin, Leibo Liu, Shaojun Wei, Shouyi Yin
2022	A*	`conf`	Upward Packet Popup for Deadlock Freedom in Modular Chiplet-Based Systems. HPCA Yibo Wu, Liang Wang, Xiaohang Wang, Jie Han, Jianfeng Zhu, Honglan Jiang, Shouyi Yin, Shaojun Wei, Leibo Liu
2021	—	`conf`	15.4 A 5.99-to-691.1TOPS/W Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity-Based Optimization and Variable-Precision Quantization. ISSCC Ruiqi Guo, Zhiheng Yue, Xin Si, Te Hu, Hao Li, Limei Tang, Yabing Wang, Leibo Liu, Meng-Fan Chang, Qiang Li, Shaojun Wei, Shouyi Yin
2021	—	`conf`	9.2A 28nm 12.1TOPS/W Dual-Mode CNN Processor Using Effective-Weight-Based Convolution and Error-Compensation-Based Prediction. ISSCC Huiyu Mo, Wenping Zhu, Wenjing Hu, Guangbin Wang, Qiang Li, Ang Li, Shouyi Yin, Shaojun Wei, Leibo Liu
2021	—	`conf`	A 28nm 276.55TFLOPS/W Sparse Deep-Neural-Network Training Processor with Implicit Redundancy Speculation and Batch Normalization Reformulation. VLSI Circuits Yang Wang, Yubin Qin, Dazheng Deng, Jingchuan Wei, Tianbao Chen, Xinhan Lin, Leibo Liu, Shaojun Wei, Shouyi Yin
2021	J	`jnl`	A 460 GOPS/W Improved Mnemonic Descent Method-Based Hardwired Accelerator for Face Alignment. IEEE Trans. Multim. Huiyu Mo, Leibo Liu, Wenping Zhu, Qiang Li, Shouyi Yin, Shaojun Wei
2021	—	`conf`	A 6.54-to-26.03 TOPS/W Computing-In-Memory RNN Processor using Input Similarity Optimization and Attention-based Context-breaking with Output Speculation. VLSI Circuits Ruiqi Guo, Hao Li, Ruhui Liu, Zhixiao Zhang, Limei Tang, Hao Sun, Leibo Liu, Meng-Fan Chang, Shaojun Wei, Shouyi Yin
2021	J	`jnl`	A Deflection-Based Deadlock Recovery Framework to Achieve High Throughput for Faulty NoCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yibo Wu, Liang Wang, Xiaohang Wang, Jie Han, Shouyi Yin, Shaojun Wei, Leibo Liu
2021	—	`conf`	A Multiple-Precision Multiply and Accumulation Design with Multiply-Add Merged Strategy for AI Accelerating. ASP-DAC Song Zhang, Jiangyuan Gu, Shouyi Yin, Leibo Liu, Shaojun Wei
2021	A*	`conf`	ABC-DIMM: Alleviating the Bottleneck of Communication in DIMM-based Near-Memory Processing with Inter-DIMM Broadcast. ISCA Weiyi Sun, Zhaoshi Li, Shouyi Yin, Shaojun Wei, Leibo Liu
2021	A*	`conf`	ADROIT: An Adaptive Dynamic Refresh Optimization Framework for DRAM Energy Saving In DNN Training. DAC Xinhan Lin, Liang Sun, Fengbin Tu, Leibo Liu, Xiangyu Li, Shaojun Wei, Shouyi Yin
2021	J	`jnl`	An Elastic Task Scheduling Scheme on Coarse-Grained Reconfigurable Architectures. IEEE Trans. Parallel Distributed Syst. Longlong Chen, Jianfeng Zhu, Yangdong Deng, Zhaoshi Li, Jian Chen, Xiaowei Jiang, Shouyi Yin, Shaojun Wei, Leibo Liu
2021	—	`conf`	Combining Memory Partitioning and Subtask Generation for Parallel Data Access on CGRAs. ASP-DAC Cheng Li, Jiangyuan Gu, Shouyi Yin, Leibo Liu, Shaojun Wei
2021	A	`conf`	Dynamic Multi-Scale Convolution for Dialect Identification. Interspeech Tianlong Kong, Shouyi Yin, Dawei Zhang, Wang Geng, Xin Wang, Dandan Song, Jinwen Huang, Huiyu Shi, Xiaorui Wang
2021	J	`jnl`	Dynamic Multi-scale Convolution for Dialect Identification. CoRR Tianlong Kong, Shouyi Yin, Dawei Zhang, Wang Geng, Xin Wang, Dandan Song, Jinwen Huang, Huiyu Shi, Xiaorui Wang
2021	J	`jnl`	Efficient Comparison and Addition for FHE With Weighted Computational Complexity Model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Neng Zhang, Qiao Qin, Zongsheng Hou, Bohan Yang, Shouyi Yin, Shaojun Wei, Leibo Liu
2021	J	`jnl`	Erratum to "Evolver: a Deep Learning Processor With On-Device Quantization-Voltage-Frequency Tuning". IEEE J. Solid State Circuits Fengbin Tu, Weiwei Wu, Yang Wang, Hongjiang Chen, Feng Xiong, Man Shi, Ning Li, Jinyi Deng, Tianbao Chen, Leibo Liu, Shaojun Wei, Yuan Xie, Shouyi Yin
2021	J	`jnl`	Evolver: A Deep Learning Processor With On-Device Quantization-Voltage-Frequency Tuning. IEEE J. Solid State Circuits Fengbin Tu, Weiwei Wu, Yang Wang, Hongjiang Chen, Feng Xiong, Man Shi, Ning Li, Jinyi Deng, Tianbao Chen, Leibo Liu, Shaojun Wei, Yuan Xie, Shouyi Yin
2021	J	`jnl`	Fast substitution-box evaluation algorithm and its efficient masking scheme for block ciphers. Sci. China Inf. Sci. Hai Huang, Leibo Liu, Min Zhu, Shouyi Yin, Shaojun Wei
2021	J	`jnl`	Flexible Rectification of a Speckle Projection System for Depth Sensing. IEEE Trans. Instrum. Meas. Kai Zhou, Shouyi Yin, Peng Ouyang, Yinan Liu, Shibin Tang
2021	A*	`conf`	FuseKNA: Fused Kernel Convolution based Accelerator for Deep Neural Networks. HPCA Jianxun Yang, Zhao Zhang, Zhuangzhi Liu, Jing Zhou, Leibo Liu, Shaojun Wei, Shouyi Yin
2021	C	`conf`	GLMSnet: Single Channel Speech Separation Framework in Noisy and Reverberant Environments. ASRU Huiyu Shi, Xi Chen, Tianlong Kong, Shouyi Yin, Peng Ouyang
2021	—	`conf`	HPPU: An Energy-Efficient Sparse DNN Training Processor with Hybrid Weight Pruning. AICAS Yang Wang, Yubin Qin, Leibo Liu, Shaojun Wei, Shouyi Yin
2021	A	`conf`	HeteroKV: A Scalable Line-rate Key-Value Store on Heterogeneous CPU-FPGA Platforms. DATE Haichang Yang, Zhaoshi Li, Jiawei Wang, Shouyi Yin, Shaojun Wei, Leibo Liu
2021	J	`jnl`	Jintide: Utilizing Low-Cost Reconfigurable External Monitors to Substantially Enhance Hardware Security of Large-Scale CPU Clusters. IEEE J. Solid State Circuits Jianfeng Zhu, Ao Luo, Guanhua Li, Bowei Zhang, Yong Wang, Gang Shan, Yi Li, Jianfeng Pan, Chenchen Deng, Shouyi Yin, Shaojun Wei, Leibo Liu
2021	—	`conf`	LPE: Logarithm Posit Processing Element for Energy-Efficient Edge-Device Training. AICAS Yang Wang, Dazheng Deng, Leibo Liu, Shaojun Wei, Shouyi Yin
2021	—	`conf`	Learnable Quantization Loss Function Based on Expectation. ICAC Hao Sun, Yujuan Cheng, Yang Wang, Bin Wang, Shouyi Yin
2021	A	`conf`	Polyhedral-based Pipelining of Imperfectly-Nested Loop for CGRAs. ICCAD Dajiang Liu, Ting Liu, Xingyu Mo, Jiaxing Shang, Shouyi Yin
2021	J	`jnl`	TIMAQ: A Time-Domain Computing-in-Memory-Based Processor Using Predictable Decomposed Convolution for Arbitrary Quantized DNNs. IEEE J. Solid State Circuits Jianxun Yang, Yuyao Kong, Zhao Zhang, Zhuangzhi Liu, Jing Zhou, Yiqi Wang, Yonggang Liu, Chenfu Guo, Te Hu, Congcong Li, Leibo Liu, Jin Zhang, Shaojun Wei, Jun Yang, Shouyi Yin
2021	—	`conf`	Towards a Secure Integrated Heterogeneous Platform via Cooperative CPU/GPU Encryption. ATS Zhendong Wang, Rujia Wang, Zihang Jiang, Xulong Tang, Shouyi Yin, Yang Hu
2020	J	`jnl`	A 2.92-Gb/s/W and 0.43-Gb/s/MG Flexible and Scalable CGRA-Based Baseband Processor for Massive MIMO Detection. IEEE J. Solid State Circuits Guiqiang Peng, Leibo Liu, Sheng Zhou, Shouyi Yin, Shaojun Wei
2020	J	`jnl`	A 4K × 2K@60fps Multifunctional Video Display Processor for High Perceptual Image Quality. IEEE Trans. Circuits Syst. I Regul. Pap. Hang Wang, Xiang Li, Daqiang Han, Shiquan Yu, Shouyi Yin, Shaojun Wei, Nanning Zheng, Xuchong Zhang, Tiancheng Wang, Wenchang Li, Qiubo Chen, Pengju Ren, Xiaogang Wu, Hongbin Sun, Zhiqiang Jiang
2020	J	`jnl`	A 60 Gb/s-Level Coarse-Grained Reconfigurable Cryptographic Processor With Less Than 1-W Power. IEEE Trans. Circuits Syst. II Express Briefs Chenchen Deng, Bo Wang, Leibo Liu, Min Zhu, Youyu Wu, Hui Li, Shouyi Yin, Shaojun Wei
2020	Misc	`conf`	A High-performance Inference Accelerator Exploiting Patterned Sparsity in CNNs. FCCM Ning Li, Leibo Liu, Shaojun Wei, Shouyi Yin
2020	J	`jnl`	A Multi-Task Hardwired Accelerator for Face Detection and Alignment. IEEE Trans. Circuits Syst. Video Technol. Huiyu Mo, Leibo Liu, Wenping Zhu, Qiang Li, Hong Liu, Shouyi Yin, Shaojun Wei
2020	—	`conf`	A Reconfigurable Branch Predictor for Spatial Computing Architectures. ICDSP Yanan Lu, Leibo Liu, Jian Liu, Shouyi Yin, Shaojun Wei
2020	J	`jnl`	A Survey of Coarse-Grained Reconfigurable Architecture and Design: Taxonomy, Challenges, and Applications. ACM Comput. Surv. Leibo Liu, Jianfeng Zhu, Zhaoshi Li, Yanan Lu, Yangdong Deng, Jie Han, Shouyi Yin, Shaojun Wei
2020	—	`conf`	A Time-Domain Computing-in-Memory based Processor using Predictable Decomposed Convolution for Arbitrary Quantized DNNs. A-SSCC Jianxun Yang, Yuyao Kong, Zhao Zhang, Zhuangzhi Liu, Jing Zhou, Yiqi Wang, Yonggang Liu, Chenfu Guo, Te Hu, Congcong Li, Leibo Liu, Jin Zhang, Shaojun Wei, Jun Yang, Shouyi Yin
2020	J	`jnl`	Achieving Flexible Global Reconfiguration in NoCs Using Reconfigurable Rings. IEEE Trans. Parallel Distributed Syst. Liang Wang, Leibo Liu, Jie Han, Xiaohang Wang, Shouyi Yin, Shaojun Wei
2020	A*	`conf`	CATCAM: Constant-time Alteration Ternary CAM with Scalable In-Memory Architecture. MICRO Dibei Chen, Zhaoshi Li, Tianzhu Xiong, Zhiwei Liu, Jun Yang, Shouyi Yin, Shaojun Wei, Leibo Liu
2020	J	`jnl`	Efficient Scheduling of Irregular Network Structures on CNN Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shixuan Zheng, Xianjue Zhang, Daoli Ou, Shibin Tang, Leibo Liu, Shaojun Wei, Shouyi Yin
2020	J	`jnl`	Enabling Latency-Aware Data Initialization for Integrated CPU/GPU Heterogeneous Platform. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zhendong Wang, Zihang Jiang, Zhen Wang, Xulong Tang, Cong Liu, Shouyi Yin, Yang Hu
2020	J	`jnl`	Energy- and Area-Efficient Recursive-Conjugate-Gradient-Based MMSE Detector for Massive MIMO Systems. IEEE Trans. Signal Process. Leibo Liu, Guiqiang Peng, Pan Wang, Sheng Zhou, Qiushi Wei, Shouyi Yin, Shaojun Wei
2020	A*	`conf`	GraphABCD: Scaling Out Graph Analytics with Asynchronous Block Coordinate Descent. ISCA Yifan Yang, Zhaoshi Li, Yangdong Deng, Zhiwei Liu, Shouyi Yin, Shaojun Wei, Leibo Liu
2020	J	`jnl`	Highly Efficient Architecture of NewHope-NIST on FPGA using Low-Complexity NTT/INTT. IACR Trans. Cryptogr. Hardw. Embed. Syst. Neng Zhang, Bohan Yang, Chen Chen, Shouyi Yin, Shaojun Wei, Leibo Liu
2020	J	`jnl`	NTTU: An Area-Efficient Low-Power NTT-Uncoupled Architecture for NTT-Based Multiplication. IEEE Trans. Computers Neng Zhang, Qiao Qin, Hang Yuan, Chenggao Zhou, Shouyi Yin, Shaojun Wei, Leibo Liu
2020	J	`jnl`	Near-Optimal MIMO-SCMA Uplink Detection With Low-Complexity Expectation Propagation. IEEE Trans. Wirel. Commun. Pan Wang, Leibo Liu, Sheng Zhou, Guiqiang Peng, Shouyi Yin, Shaojun Wei
2020	Misc	`conf`	PAGAN: A Phase-Adapted Generative Adversarial Networks for Speech Enhancement. ICASSP Peishuo Li, Zihang Jiang, Shouyi Yin, Dandan Song, Peng Ouyang, Leibo Liu, Shaojun Wei
2020	J	`jnl`	Pattern-Based Dynamic Compilation System for CGRAs With Online Configuration Transformation. IEEE Trans. Parallel Distributed Syst. Leibo Liu, Xingchen Man, Jianfeng Zhu, Shouyi Yin, Shaojun Wei
2020	A*	`conf`	STC: Significance-aware Transform-based Codec Framework for External Memory Access Reduction. DAC Feng Xiong, Fengbin Tu, Man Shi, Yang Wang, Leibo Liu, Shaojun Wei, Shouyi Yin
2020	A*	`conf`	TAEM: Fast Transfer-Aware Effective Loop Mapping for Heterogeneous Resources on CGRA. DAC Mingyang Kou, Jiangyuan Gu, Shaojun Wei, Hailong Yao, Shouyi Yin
2020	A*	`conf`	TFE: Energy-efficient Transferred Filter-based Engine to Compress and Accelerate Convolutional Neural Networks. MICRO Huiyu Mo, Leibo Liu, Wenjing Hu, Wenping Zhu, Qiang Li, Ang Li, Shouyi Yin, Jian Chen, Xiaowei Jiang, Shaojun Wei
2020	A	`conf`	THUEE System for NIST SRE19 CTS Challenge. INTERSPEECH Ruyun Li, Tianyu Liang, Dandan Song, Yi Liu, Yangcheng Wu, Can Xu, Peng Ouyang, Xianwei Zhang, Xianhong Chen, Weiqiang Zhang, Shouyi Yin, Liang He
2020	A	`conf`	Transformer with Bidirectional Decoder for Speech Recognition. INTERSPEECH Xi Chen, Songyang Zhang, Dandan Song, Peng Ouyang, Shouyi Yin
2020	J	`jnl`	Transformer with Bidirectional Decoder for Speech Recognition. CoRR Xi Chen, Songyang Zhang, Dandan Song, Peng Ouyang, Shouyi Yin
2019	—	`conf`	A 5.1pJ/Neuron 127.3us/Inference RNN-based Speech Recognition Processor using 16 Computing-in-Memory SRAM Macros in 65nm CMOS. VLSI Circuits Ruiqi Guo, Yonggang Liu, Shixuan Zheng, Ssu-Yen Wu, Peng Ouyang, Win-San Khwa, Xi Chen, Jia-Jing Chen, Xiudong Li, Leibo Liu, Meng-Fan Chang, Shaojun Wei, Shouyi Yin
2019	J	`jnl`	A Binary-Feature-Based Object Recognition Accelerator With 22 M-Vector/s Throughput and 0.68 G-Vector/J Energy-Efficiency for Full-HD Resolution. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Leibo Liu, Wenping Zhu, Shouyi Yin, Shaojun Wei
2019	J	`jnl`	A Face Alignment Accelerator Based on Optimized Coarse-to-Fine Shape Searching. IEEE Trans. Circuits Syst. Video Technol. Leibo Liu, Qiang Wang, Wenping Zhu, Huiyu Mo, Tianchen Wang, Shouyi Yin, Yiyu Shi, Shaojun Wei
2019	J	`jnl`	A Fast and Power-Efficient Hardware Architecture for Non-Maximum Suppression. IEEE Trans. Circuits Syst. II Express Briefs Man Shi, Peng Ouyang, Shouyi Yin, Leibo Liu, Shaojun Wei
2019	J	`jnl`	A High Throughput Acceleration for Hybrid Neural Networks With Efficient Resource Management on FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shouyi Yin, Shibin Tang, Xinhan Lin, Peng Ouyang, Fengbin Tu, Leibo Liu, Shaojun Wei
2019	J	`jnl`	A Lifetime Reliability-Constrained Runtime Mapping for Throughput Optimization in Many-Core Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Liang Wang, Ping Lv, Leibo Liu, Jie Han, Ho-fung Leung, Xiaohang Wang, Shouyi Yin, Shaojun Wei, Terrence S. T. Mak
2019	C	`conf`	A Reliable Physical Unclonable Function Based on Differential Charging Capacitors. ISCAS Hang Yuan, Wei Guo, Chip-Hong Chang, Yuan Cao, Shaojun Wei, Shouyi Yin, Chenchen Deng, Leibo Liu, Wei Ge, Fan Zhang
2019	—	`conf`	A Skyrmion Racetrack Memory based Computing In-memory Architecture for Binary Neural Convolutional Network. ACM Great Lakes Symposium on VLSI Yu Pan, Peng Ouyang, Yinglin Zhao, Shouyi Yin, Youguang Zhang, Shaojun Wei, Weisheng Zhao
2019	—	`conf`	An Energy-Efficient Architecture for Accelerating Inference of Memory-Augmented Neural Networks. NANOARCH Jianxun Yang, Leibo Liu, Jin Zhang, Shaojun Wei, Shouyi Yin
2019	J	`jnl`	An Energy-Efficient Reconfigurable Processor for Binary-and Ternary-Weight Neural Networks With Flexible Data Bit Width. IEEE J. Solid State Circuits Shouyi Yin, Peng Ouyang, Jianxun Yang, Tianyi Lu, Xiudong Li, Leibo Liu, Shaojun Wei
2019	J	`jnl`	An STT-MRAM Based in Memory Architecture for Low Power Integral Computing. IEEE Trans. Computers Yinglin Zhao, Peng Ouyang, Wang Kang, Shouyi Yin, Youguang Zhang, Shaojun Wei, Weisheng Zhao
2019	J	`jnl`	An Ultra-Low Power Binarized Convolutional Neural Network-Based Speech Recognition Processor With On-Chip Self-Learning. IEEE Trans. Circuits Syst. I Regul. Pap. Shixuan Zheng, Peng Ouyang, Dandan Song, Xiudong Li, Leibo Liu, Shaojun Wei, Shouyi Yin
2019	A	`conf`	Constructing Concurrent Data Structures on FPGA with Channels. FPGA Hui Yan, Zhaoshi Li, Leibo Liu, Shouyi Yin, Shaojun Wei
2019	J	`jnl`	Data-Flow Graph Mapping Optimization for CGRA With Deep Reinforcement Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Dajiang Liu, Shouyi Yin, Guojie Luo, Jiaxing Shang, Leibo Liu, Shaojun Wei, Yong Feng, Shangbo Zhou
2019	A*	`conf`	FPGA-Accelerated Optimistic Concurrency Control for Transactional Memory. MICRO Zhaoshi Li, Leibo Liu, Yangdong Deng, Jiawei Wang, Zhiwei Liu, Shouyi Yin, Shaojun Wei
2019	J	`jnl`	Face Alignment With Expression- and Pose-Based Adaptive Initialization. IEEE Trans. Multim. Huiyu Mo, Leibo Liu, Wenping Zhu, Shouyi Yin, Shaojun Wei
2019	—	`conf`	Jintide®: A Hardware Security Enhanced Server CPU with Xeon® Cores under Runtime Surveillance by an In-Package Dynamically Reconfigurable Processor. Hot Chips Symposium Leibo Liu, Ao Luo, Guanhua Li, Jianfeng Zhu, Yong Wang, Gang Shan, Jianfeng Pan, Shouyi Yin, Shaojun Wei
2019	J	`jnl`	Low Area-Overhead Low-Entropy Masking Scheme (LEMS) Against Correlation Power Analysis Attack. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hai Huang, Leibo Liu, Qihuan Huang, Yingjie Chen, Shouyi Yin, Shaojun Wei
2019	—	`conf`	MoNA: Mobile Neural Architecture with Reconfigurable Parallel Dimensions. NEWCAS Weiwei Wu, Shouyi Yin, Fengbin Tu, Leibo Liu, Shaojun Wei
2019	J	`jnl`	Parana: A Parallel Neural Architecture Considering Thermal Problem of 3D Stacked Memory. IEEE Trans. Parallel Distributed Syst. Shouyi Yin, Shibin Tang, Xinhan Lin, Peng Ouyang, Fengbin Tu, Leibo Liu, Jishen Zhao, Cong Xu, Shuangchen Li, Yuan Xie, Shaojun Wei
2019	A	`conf`	ReDESK: A Reconfigurable Dataflow Engine for Sparse Kernels on Heterogeneous Platforms. ICCAD Kai Lu, Zhaoshi Li, Leibo Liu, Jiawei Wang, Shouyi Yin, Shaojun Wei
2019	J	`jnl`	Reconfigurable Architecture for Neural Approximation in Multimedia Computing. IEEE Trans. Circuits Syst. Video Technol. Fengbin Tu, Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei
2019	—	`conf`	Sandwich-RAM: An Energy-Efficient In-Memory BWN Architecture with Pulse-Width Modulation. ISSCC Jun Yang, Yuyao Kong, Zhen Wang, Yan Liu, Bo Wang, Shouyi Yin, Longxin Shi
2019	C	`conf`	Small-Footprint Keyword Spotting with Graph Convolutional Network. ASRU Xi Chen, Shouyi Yin, Dandan Song, Peng Ouyang, Leibo Liu, Shaojun Wei
2019	J	`jnl`	Small-footprint Keyword Spotting with Graph Convolutional Network. CoRR Xi Chen, Shouyi Yin, Dandan Song, Peng Ouyang, Leibo Liu, Shaojun Wei
2019	J	`jnl`	THUEE system description for NIST 2019 SRE CTS Challenge. CoRR Yi Liu, Tianyu Liang, Can Xu, Xianwei Zhang, Xianhong Chen, Wei-Qiang Zhang, Liang He, Dandan Song, Ruyun Li, Yangcheng Wu, Peng Ouyang, Shouyi Yin
2019	—	`conf`	Towards Efficient Compact Network Training on Edge-Devices. ISVLSI Feng Xiong, Fengbin Tu, Shouyi Yin, Shaojun Wei
2018	J	`jnl`	A 1.58 Gbps/W 0.40 Gbps/mm2 ASIC Implementation of MMSE Detection for $128\times 8~64$ -QAM Massive MIMO in 65 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Guiqiang Peng, Leibo Liu, Sheng Zhou, Shouyi Yin, Shaojun Wei
2018	—	`conf`	A 141 UW, 2.46 PJ/Neuron Binarized Convolutional Neural Network Based Self-Learning Speech Recognition Processor in 28NM CMOS. VLSI Circuits Shouyi Yin, Peng Ouyang, Shixuan Zheng, Dandan Song, Xiudong Li, Leibo Liu, Shaojun Wei
2018	—	`conf`	A 2.69 Mbps/mW 1.09 Mbps/kGE Conjugate Gradient-based MMSE Detector for 64-QAM 128×8 Massive MIMO Systems. A-SSCC Guiqiang Peng, Leibo Liu, Qiushi Wei, Yao Wang, Shouyi Yin, Shaojun Wei
2018	—	`conf`	A 4K×2K@60fps Multi-format Multi-function Display Processor for High Perceptual Quality. APCCAS Hang Wang, Hongbin Sun, Xuchong Zhang, Qiubo Chen, Pengju Ren, Xiaogang Wu, Shouyi Yin, Zhiqiang Jiang, Xiang Li, Daqiang Han, Shiquan Yu, Shaojun Wei, Nanning Zheng
2018	J	`jnl`	A Fast and Power-Efficient Hardware Architecture for Visual Feature Detection in Affine-SIFT. IEEE Trans. Circuits Syst. I Regul. Pap. Peng Ouyang, Shouyi Yin, Leibo Liu, Youguang Zhang, Weisheng Zhao, Shaojun Wei
2018	—	`conf`	A Full Multicast Reconfigurable Non-blocking Permutation Network. CyberC Hang Yuan, Leibo Liu, Hui Li, Shouyi Yin, Shaojun Wei
2018	J	`jnl`	A High Energy Efficient Reconfigurable Hybrid Neural Network Processor for Deep Learning Applications. IEEE J. Solid State Circuits Shouyi Yin, Peng Ouyang, Shibin Tang, Fengbin Tu, Xiudong Li, Shixuan Zheng, Tianyi Lu, Jiangyuan Gu, Leibo Liu, Shaojun Wei
2018	J	`jnl`	Algorithm and Architecture of a Low-Complexity and High-Parallelism Preprocessing-Based K -Best Detector for Large-Scale MIMO Systems. IEEE Trans. Signal Process. Guiqiang Peng, Leibo Liu, Sheng Zhou, Yang Xue, Shouyi Yin, Shaojun Wei
2018	C	`conf`	An Energy Efficient JPEG Encoder with Neural Network Based Approximation and Near-Threshold Computing. ISCAS Zhihui Wang, Shouyi Yin, Fengbin Tu, Leibo Liu, Shaojun Wei
2018	—	`conf`	An Ultra-High Energy-Efficient Reconfigurable Processor for Deep Neural Networks with Binary/Ternary Weights in 28NM CMOS. VLSI Circuits Shouyi Yin, Peng Ouyang, Jianxun Yang, Tianyi Lu, Xiudong Li, Leibo Liu, Shaojun Wei
2018	A*	`conf`	An efficient kernel transformation architecture for binary- and ternary-weight neural network inference. DAC Shixuan Zheng, Yonggang Liu, Shouyi Yin, Leibo Liu, Shaojun Wei
2018	J	`jnl`	Anole: A Highly Efficient Dynamically Reconfigurable Crypto-Processor for Symmetric-Key Algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Leibo Liu, Bo Wang, Chenchen Deng, Min Zhu, Shouyi Yin, Shaojun Wei
2018	J	`jnl`	Bit-Level Disturbance-Aware Memory Partitioning for Parallel Data Access for MLC STT-RAM. IEEE Trans. Very Large Scale Integr. Syst. Shouyi Yin, Tianyi Lu, Zhicong Xie, Leibo Liu, Shaojun Wei
2018	C	`conf`	Bit-width Adaptive Accelerator Design for Convolution Neural Network. ISCAS Jianxin Guo, Shouyi Yin, Peng Ouyang, Fengbin Tu, Shibin Tang, Leibo Liu, Shaojun Wei
2018	J	`jnl`	Breaking the Synchronization Bottleneck with Reconfigurable Transactional Execution. IEEE Comput. Archit. Lett. Zhaoshi Li, Leibo Liu, Yangdong Deng, Shouyi Yin, Shaojun Wei
2018	J	`jnl`	CDPM: Context-Directed Pattern Matching Prefetching to Improve Coarse-Grained Reconfigurable Array Performance. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Leibo Liu, Chen Yang, Shouyi Yin, Shaojun Wei
2018	J	`jnl`	DRMaSV: Enhanced Capability Against Hardware Trojans in Coarse Grained Reconfigurable Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Leibo Liu, Zhuoquan Zhou, Shaojun Wei, Min Zhu, Shouyi Yin, Shengyang Mao
2018	—	`conf`	Efficient Hardware Architecture of Softmax Layer in Deep Neural Network. DSP Ruofei Hu, Binren Tian, Shouyi Yin, Shaojun Wei
2018	J	`jnl`	FP-BNN: Binarized neural network on FPGA. Neurocomputing Shuang Liang, Shouyi Yin, Leibo Liu, Wayne Luk, Shaojun Wei
2018	J	`jnl`	GNA: Reconfigurable and Efficient Architecture for Generative Network Acceleration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jiale Yan, Shouyi Yin, Fengbin Tu, Leibo Liu, Shaojun Wei
2018	J	`jnl`	HReA: An Energy-Efficient Embedded Dynamically Reconfigurable Fabric for 13-Dwarfs Processing. IEEE Trans. Circuits Syst. II Express Briefs Leibo Liu, Zhaoshi Li, Chen Yang, Chenchen Deng, Shouyi Yin, Shaojun Wei
2018	A*	`conf`	LCP: a layer clusters paralleling mapping method for accelerating inception and residual networks on FPGA. DAC Xinhan Lin, Shouyi Yin, Fengbin Tu, Leibo Liu, Xiangyu Li, Shaojun Wei
2018	J	`jnl`	Memory Partitioning for Parallel Multipattern Data Access in Multiple Data Arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shouyi Yin, Zhicong Xie, Chenyue Meng, Peng Ouyang, Leibo Liu, Shaojun Wei
2018	J	`jnl`	Multi-Bank Memory Aware Force Directed Scheduling for High-Level Synthesis. IEEE Access Shouyi Yin, Tianyi Lu, Xianqing Yao, Zhicong Xie, Leibo Liu, Shaojun Wei
2018	J	`jnl`	Optimization of Softmax Layer in Deep Neural Network Using Integral Stochastic Computation. J. Low Power Electron. Ruofei Hu, Binren Tian, Shouyi Yin, Shaojun Wei
2018	A*	`conf`	RANA: Towards Efficient Neural Acceleration with Refresh-Optimized Embedded DRAM. ISCA Fengbin Tu, Weiwei Wu, Shouyi Yin, Leibo Liu, Shaojun Wei
2018	J	`jnl`	Stress-Aware Loops Mapping on CGRAs with Dynamic Multi-Map Reconfiguration. IEEE Trans. Parallel Distributed Syst. Jiangyuan Gu, Shouyi Yin, Leibo Liu, Shaojun Wei
2018	J	`jnl`	Triggered-Issuance and Triggered-Execution: A Control Paradigm to Minimize Pipeline Stalls in Distributed Controlled Coarse-Grained Reconfigurable Arrays. IEEE Trans. Parallel Distributed Syst. Yanan Lu, Leibo Liu, Yangdong Deng, Jian Weng, Shouyi Yin, Yiyu Shi, Shaojun Wei
2017	A*	`conf`	A Fast and Power Efficient Architecture to Parallelize LSTM based RNN for Cognitive Intelligence Applications. DAC Peng Ouyang, Shouyi Yin, Shaojun Wei
2017	J	`jnl`	A Multi-Objective Model Oriented Mapping Approach for NoC-based Computing Systems. IEEE Trans. Parallel Distributed Syst. Chen Wu, Chenchen Deng, Leibo Liu, Jie Han, Jiqiang Chen, Shouyi Yin, Shaojun Wei
2017	—	`conf`	A Power Efficient Architecture with Optimized Parallel Memory Accessing for Feature Generation. ACM Great Lakes Symposium on VLSI Peng Ouyang, Shouyi Yin, Chunxiao Xing, Leibo Liu, Shaojun Wei
2017	—	`conf`	AEPE: An area and power efficient RRAM crossbar-based accelerator for deep CNNs. NVMSA Shibin Tang, Shouyi Yin, Shixuan Zheng, Peng Ouyang, Fengbin Tu, Leiyue Yao, Jinzhou Wu, Wenming Cheng, Leibo Liu, Shaojun Wei
2017	A*	`conf`	Aggressive Pipelining of Irregular Applications on Reconfigurable Hardware. ISCA Zhaoshi Li, Leibo Liu, Yangdong Deng, Shouyi Yin, Yao Wang, Shaojun Wei
2017	J	`jnl`	An AdaBoost-Based Face Detection System Using Parallel Configurable Architecture With Optimized Computation. IEEE Syst. J. Shouyi Yin, Peng Ouyang, Xu Dai, Leibo Liu, Shaojun Wei
2017	Misc	`conf`	Bit-Width Based Resource Partitioning for CNN Acceleration on FPGA. FCCM Jianxin Guo, Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei
2017	J	`jnl`	CIACP: A Correlation- and Iteration- Aware Cache Partitioning Mechanism to Improve Performance of Multiple Coarse-Grained Reconfigurable Arrays. IEEE Trans. Parallel Distributed Syst. Chen Yang, Leibo Liu, Kai Luo, Shouyi Yin, Shaojun Wei
2017	J	`jnl`	Conflict-Free Loop Mapping for Coarse-Grained Reconfigurable Architecture with Multi-Bank Memory. IEEE Trans. Parallel Distributed Syst. Shouyi Yin, Xianqing Yao, Tianyi Lu, Dajiang Liu, Jiangyuan Gu, Leibo Liu, Shaojun Wei
2017	C	`conf`	DFGNet: Mapping dataflow graph onto CGRA by a deep learning approach. ISCAS Shouyi Yin, Dajiang Liu, Lifeng Sun, Leibo Liu, Shaojun Wei
2017	J	`jnl`	Deep Convolutional Neural Network Architecture With Reconfigurable Computation Patterns. IEEE Trans. Very Large Scale Integr. Syst. Fengbin Tu, Shouyi Yin, Peng Ouyang, Shibin Tang, Leibo Liu, Shaojun Wei
2017	A*	`conf`	Disturbance Aware Memory Partitioning for Parallel Data Access in STT-RAM. DAC Shouyi Yin, Zhicong Xie, Shaojun Wei
2017	—	`conf`	Energy-aware loops mapping on multi-vdd CGRAs without performance degradation. ASP-DAC Jiangyuan Gu, Shouyi Yin, Leibo Liu, Shaojun Wei
2017	J	`jnl`	Exploration of Benes Network in Cryptographic Processors: A Random Infection Countermeasure for Block Ciphers Against Fault Attacks. IEEE Trans. Inf. Forensics Secur. Bo Wang, Leibo Liu, Chenchen Deng, Min Zhu, Shouyi Yin, Zhuoquan Zhou, Shaojun Wei
2017	J	`jnl`	Implementation of in-loop filter for HEVC decoder on reconfigurable processor. IET Image Process. Leibo Liu, Yingjie Chen, Chenchen Deng, Shouyi Yin, Shaojun Wei
2017	A	`conf`	Joint Modulo Scheduling and Memory Partitioning with Multi-Bank Memory for High-Level Synthesis (Abstract Only). FPGA Tianyi Lu, Shouyi Yin, Xianqing Yao, Zhicong Xie, Leibo Liu, Shaojun Wei
2017	A	`conf`	Learning Convolutional Neural Networks for Data-Flow Graph Mapping on Spatial Programmable Architectures (Abstract Only). FPGA Shouyi Yin, Dajiang Liu, Lifeng Sun, Xinhan Lin, Leibo Liu, Shaojun Wei
2017	J	`jnl`	Low-Computing-Load, High-Parallelism Detection Method Based on Chebyshev Iteration for Massive MIMO Systems With VLSI Architecture. IEEE Trans. Signal Process. Guiqiang Peng, Leibo Liu, Peng Zhang, Shouyi Yin, Shaojun Wei
2017	C	`conf`	Memory fartitioning-based modulo scheduling for high-level synthesis. ISCAS Tianyi Lu, Shouyi Yin, Xianqing Yao, Zhicong Xie, Leibo Liu, Shaojun Wei
2017	Misc	`conf`	Multi-CNN and decision tree based driving behavior evaluation. SAC Shouyi Yin, Jinjin Duan, Peng Ouyang, Leibo Liu, Shaojun Wei
2017	J	`jnl`	PMCC: Fast and Accurate System-Level Power Modeling for Processors on Heterogeneous SoC. IEEE Trans. Circuits Syst. II Express Briefs Chenchen Deng, Leibo Liu, Yang Liu, Shouyi Yin, Shaojun Wei
2017	J	`jnl`	Reconfigurable VLSI Architecture for Real-Time 2D-to-3D Conversion. IEEE Access Weizhi Xu, Shouyi Yin, Zhen Zhang, Hao Dong, Rui Shi, Leibo Liu, Shaojun Wei
2017	A*	`conf`	Stress-Aware Loops Mapping on CGRAs with Considering NBTI Aging Effect. DAC Jiangyuan Gu, Shouyi Yin, Shaojun Wei
2016	J	`jnl`	A 135-frames/s 1080p 87.5-mW Binary-Descriptor-Based Image Feature Extraction Accelerator. IEEE Trans. Circuits Syst. Video Technol. Wenping Zhu, Leibo Liu, Guangli Jiang, Shouyi Yin, Shaojun Wei
2016	J	`jnl`	A Coarse-Grained Reconfigurable Architecture for Compute-Intensive MapReduce Acceleration. IEEE Comput. Archit. Lett. Shuang Liang, Shouyi Yin, Leibo Liu, Yike Guo, Shaojun Wei
2016	J	`jnl`	A Configurable Parallel Hardware Architecture for Efficient Integral Histogram Image Computing. IEEE Trans. Very Large Scale Integr. Syst. Shouyi Yin, Peng Ouyang, Tianbao Chen, Leibo Liu, Shaojun Wei
2016	J	`jnl`	A Fast and Power-Efficient Memory-Centric Architecture for Affine Computation. IEEE Trans. Circuits Syst. II Express Briefs Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei
2016	J	`jnl`	A fast face detection architecture for auto-focus in smart-phones and digital cameras. Sci. China Inf. Sci. Peng Ouyang, Shouyi Yin, Chenchen Deng, Leibo Liu, Shaojun Wei
2016	J	`jnl`	Against Double Fault Attacks: Injection Effort Model, Space and Time Randomization Based Countermeasures for Reconfigurable Array Architecture. IEEE Trans. Inf. Forensics Secur. Bo Wang, Leibo Liu, Chenchen Deng, Min Zhu, Shouyi Yin, Shaojun Wei
2016	J	`jnl`	An Implementation of Multiple-Standard Video Decoder on a Mixed-Grained Reconfigurable Computing Platform. IEICE Trans. Inf. Syst. Leibo Liu, Dong Wang, Yingjie Chen, Min Zhu, Shouyi Yin, Shaojun Wei
2016	J	`jnl`	CWFP: Novel Collective Writeback and Fill Policy for Last-Level DRAM Cache. IEEE Trans. Very Large Scale Integr. Syst. Shouyi Yin, Weizhi Xu, Jiakun Li, Leibo Liu, Shaojun Wei
2016	A*	`conf`	Data cache prefetching via context directed pattern matching for coarse-grained reconfigurable arrays. DAC Chen Yang, Leibo Liu, Shouyi Yin, Shaojun Wei
2016	—	`conf`	Energy management on DVS based coarse-grained reconfigurable platform. NANOARCH Peng Ouyang, Shouyi Yin, Chunxiao Xing, Leibo Liu, Shaojun Wei
2016	J	`jnl`	Exploiting Parallelism of Imperfect Nested Loops on Coarse-Grained Reconfigurable Architectures. IEEE Trans. Parallel Distributed Syst. Shouyi Yin, Xinhan Lin, Leibo Liu, Shaojun Wei
2016	—	`conf`	Exploiting parallelism of imperfect nested loops with sibling inner loops on coarse-grained reconfigurable architectures. ASP-DAC Xinhan Lin, Shouyi Yin, Leibo Liu, Shaojun Wei
2016	J	`jnl`	Improving Nested Loop Pipelining on Coarse-Grained Reconfigurable Architectures. IEEE Trans. Very Large Scale Integr. Syst. Shouyi Yin, Dajiang Liu, Yu Peng, Leibo Liu, Shaojun Wei
2016	J	`jnl`	Joint Modulo Scheduling and V IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shouyi Yin, Jiangyuan Gu, Dajiang Liu, Leibo Liu, Shaojun Wei
2016	A	`conf`	Joint loop mapping and data placement for coarse-grained reconfigurable architecture with multi-bank memory. ICCAD Shouyi Yin, Xianqing Yao, Tianyi Lu, Leibo Liu, Shaojun Wei
2016	J	`jnl`	Memory-Aware Loop Mapping on Coarse-Grained Reconfigurable Architectures. IEEE Trans. Very Large Scale Integr. Syst. Shouyi Yin, Xianqing Yao, Dajiang Liu, Leibo Liu, Shaojun Wei
2016	A	`conf`	Multibank memory optimization for parallel data access in multiple data arrays. ICCAD Shouyi Yin, Zhicong Xie, Chenyue Meng, Leibo Liu, Shaojun Wei
2016	J	`jnl`	TLIA: Efficient Reconfigurable Architecture for Control-Intensive Kernels with Triggered-Long-Instructions. IEEE Trans. Parallel Distributed Syst. Leibo Liu, Junbin Wang, Jianfeng Zhu, Chenchen Deng, Shouyi Yin, Shaojun Wei
2016	J	`jnl`	Trigger-Centric Loop Mapping on CGRAs. IEEE Trans. Very Large Scale Integr. Syst. Shouyi Yin, Pengcheng Zhou, Leibo Liu, Shaojun Wei
2015	A*	`conf`	A 127 fps in full hd accelerator based on optimized AKAZE with efficiency and effectiveness for image feature extraction. DAC Guangli Jiang, Leibo Liu, Wenping Zhu, Shouyi Yin, Shaojun Wei
2015	J	`jnl`	A 181 GOPS AKAZE Accelerator Employing Discrete-Time Cellular Neural Networks for Real-Time Feature Extraction. Sensors Guangli Jiang, Leibo Liu, Wenping Zhu, Shouyi Yin, Shaojun Wei
2015	—	`conf`	A 83fps 1080P resolution 354 mW silicon implementation for computing the improved robust feature in affine space. CICC Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei
2015	J	`jnl`	A Fast Integral Image Computing Hardware Architecture With High Power and Area Efficiency. IEEE Trans. Circuits Syst. II Express Briefs Peng Ouyang, Shouyi Yin, Yuchi Zhang, Leibo Liu, Shaojun Wei
2015	J	`jnl`	A Flexible Energy- and Reliability-Aware Application Mapping for NoC-Based Reconfigurable Architectures. IEEE Trans. Very Large Scale Integr. Syst. Leibo Liu, Chen Wu, Chenchen Deng, Shouyi Yin, Qinghua Wu, Jie Han, Shaojun Wei
2015	J	`jnl`	A Hybrid Reconfigurable Architecture and Design Methods Aiming at Control-Intensive Kernels. IEEE Trans. Very Large Scale Integr. Syst. Jianfeng Zhu, Leibo Liu, Shouyi Yin, Xiao Yang, Shaojun Wei
2015	A	`conf`	A Mixed-Grained Reconfigurable Computing Platform for Multiple-Standard Video Decoding (Abstract Only). FPGA Leibo Liu, Yingjie Victor Chen, Dong Wang, Min Zhu, Shouyi Yin, Shaojun Wei
2015	A	`conf`	A Multi-modal 2D + 3D Face Recognition Method with a Novel Local Feature Descriptor. WACV Xu Dai, Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei
2015	J	`jnl`	A Novel 2D-to-3D Video Conversion Method Using Time-Coherent Depth Maps. Sensors Shouyi Yin, Hao Dong, Guangli Jiang, Leibo Liu, Shaojun Wei
2015	A	`conf`	A Novel Composite Method to Accelerate Control Flow on Reconfigurable Architecture (Abstract Only). FPGA Junbin Wang, Leibo Liu, Jianfeng Zhu, Shouyi Yin, Shaojun Wei
2015	—	`conf`	A novel approach using a minimum cost maximum flow algorithm for fault-tolerant topology reconfiguration in NoC architectures. ASP-DAC Leibo Liu, Yu Ren, Chenchen Deng, Shouyi Yin, Shaojun Wei, Jie Han
2015	J	`jnl`	A real-time time-consistent 2D-to-3D video conversion system using color histogram. IEEE Trans. Consumer Electron. Zhen Zhang, Shouyi Yin, Leibo Liu, Shaojun Wei
2015	A	`conf`	Acceleration of Nested Conditionals on CGRAs via Trigger Scheme. ICCAD Shouyi Yin, Pengcheng Zhou, Leibo Liu, Shaojun Wei
2015	A*	`conf`	Acceleration of control flows on reconfigurable architecture with a composite method. DAC Junbin Wang, Leibo Liu, Jianfeng Zhu, Shouyi Yin, Shaojun Wei
2015	J	`jnl`	An Efficient Application Mapping Approach for the Co-Optimization of Reliability, Energy, and Performance in Reconfigurable NoC Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chen Wu, Chenchen Deng, Leibo Liu, Jie Han, Jiqiang Chen, Shouyi Yin, Shaojun Wei
2015	J	`jnl`	An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding. IEEE Trans. Multim. Leibo Liu, Dong Wang, Min Zhu, Yansheng Wang, Shouyi Yin, Peng Cao, Jun Yang, Shaojun Wei
2015	C	`conf`	An automatic depth map generation method by image classification. ICCE Hao Dong, Shouyi Yin, Guangli Jiang, Leibo Liu, Shaojun Wei
2015	J	`jnl`	Battery-Aware Loop Nests Mapping for CGRAs. IEICE Trans. Inf. Syst. Yu Peng, Shouyi Yin, Leibo Liu, Shaojun Wei
2015	—	`conf`	Battery-aware mapping optimization of loop nests for CGRAs. ASP-DAC Yu Peng, Shouyi Yin, Leibo Liu, Shaojun Wei
2015	J	`jnl`	Configuration Approaches to Enhance Computing Efficiency of Coarse-Grained Reconfigurable Array. J. Circuits Syst. Comput. Chen Yang, Leibo Liu, Yansheng Wang, Shouyi Yin, Peng Cao, Shaojun Wei
2015	A	`conf`	Cooperatively managing dynamic writeback and insertion policies in a last-level DRAM cache. DATE Shouyi Yin, Jiakun Li, Leibo Liu, Shaojun Wei, Yike Guo
2015	J	`jnl`	Correction to "An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding". IEEE Trans. Multim. Leibo Liu, Dong Wang, Min Zhu, Yansheng Wang, Shouyi Yin, Peng Cao, Jun Yang, Shaojun Wei
2015	A	`conf`	Cost-Effective Memory Architecture to Achieve Flexible Configuration and Efficient Data Transmission for Coarse-Grained Reconfigurable Array (Abstract Only). FPGA Chen Yang, Leibo Liu, Shouyi Yin, Shaojun Wei
2015	J	`jnl`	Efficient Fault-Tolerant Topology Reconfiguration Using a Maximum Flow Algorithm. ACM Trans. Reconfigurable Technol. Syst. Yu Ren, Leibo Liu, Shouyi Yin, Jie Han, Shaojun Wei
2015	C	`conf`	Efficient lane detection system based on monocular camera. ICCE Tao Tan, Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei
2015	A*	`conf`	Efficient memory partitioning for parallel data access in multidimensional arrays. DAC Chenyue Meng, Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei
2015	J	`jnl`	Energy Management on Battery-Powered Coarse-Grained Reconfigurable Platforms. IEEE Trans. Very Large Scale Integr. Syst. Peng Ouyang, Shouyi Yin, Leibo Liu, Shaojun Wei
2015	J	`jnl`	Fast Traffic Sign Recognition with a Rotation Invariant Binary Pattern Based Feature. Sensors Shouyi Yin, Peng Ouyang, Leibo Liu, Yike Guo, Shaojun Wei
2015	J	`jnl`	High-Performance Motion Estimation for Image Sensors with Video Compression. Sensors Weizhi Xu, Shouyi Yin, Leibo Liu, Zhiyong Liu, Shaojun Wei
2015	A	`conf`	Joint affine transformation and loop pipelining for mapping nested loop on CGRAs. DATE Shouyi Yin, Dajiang Liu, Leibo Liu, Shaojun Wei, Yike Guo
2015	J	`jnl`	Low-Power Loop Parallelization onto CGRA Utilizing Variable Dual V IEICE Trans. Inf. Syst. Bing Xu, Shouyi Yin, Leibo Liu, Shaojun Wei
2015	J	`jnl`	Mapping Multi-Level Loop Nests onto CGRAs Using Polyhedral Optimizations. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Dajiang Liu, Shouyi Yin, Leibo Liu, Shaojun Wei
2015	C	`conf`	Neural approximating architecture targeting multiple application domains. ISCAS Fengbin Tu, Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei
2015	J	`jnl`	Optimizing Spatial Mapping of Nested Loop for Coarse-Grained Reconfigurable Architectures. IEEE Trans. Very Large Scale Integr. Syst. Dajiang Liu, Shouyi Yin, Yu Peng, Leibo Liu, Shaojun Wei
2015	A	`conf`	RNA: a reconfigurable architecture for hardware neural acceleration. DATE Fengbin Tu, Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei
2015	C	`conf`	Real-time time-consistent 2D-to-3D video conversion based on color histogram. ICCE Zhen Zhang, Shouyi Yin, Leibo Liu, Shaojun Wei
2015	J	`jnl`	Reliability-aware mapping for various NoC topologies and routing algorithms under performance constraints. Sci. China Inf. Sci. Chen Wu, Chenchen Deng, Leibo Liu, Shouyi Yin, Jie Han, Shaojun Wei
2015	J	`jnl`	The Implementation of Texture-Based Video Up-Scaling on Coarse-Grained Reconfigurable Architecture. IEICE Trans. Inf. Syst. Rui Shi, Shouyi Yin, Leibo Liu, Qiongbing Liu, Shuang Liang, Shaojun Wei
2014	J	`jnl`	A 1/2.5 inch VGA 400 fps CMOS Image Sensor With High Sensitivity for Machine Vision. IEEE J. Solid State Circuits Ruoyu Xu, Wai Chiu Ng, George Jie Yuan, Shouyi Yin, Shaojun Wei
2014	C	`conf`	A 65 nm uneven-dual-core SoC based platform for multi-device collaborative computing. ISCAS Wenping Zhu, Leibo Liu, Shouyi Yin, Yuan Dong, Shaojun Wei, Eugene Y. Tang, Jiqiang Song, Jinzhan Peng
2014	B	`conf`	A FAST Extreme Illumination Robust Feature in Affine Space. ICPR Peng Ouyang, Shouyi Yin, Leibo Liu, Shaojun Wei
2014	J	`jnl`	A Multi-Modal Face Recognition Method Using Complete Local Derivative Patterns and Depth Maps. Sensors Shouyi Yin, Xu Dai, Peng Ouyang, Leibo Liu, Shaojun Wei
2014	—	`conf`	A fast and robust traffic sign recognition method using ring of RIBP histograms based feature. ROBIO Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei
2014	C	`conf`	A parallel hardware architecture for fast integral image computing. ISCAS Yuchi Zhang, Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei
2014	J	`jnl`	An uneven-dual-core processor based mobile platform for facilitating the collaboration among various embedded electronic devices. IEEE Trans. Consumer Electron. Leibo Liu, Wenping Zhu, Shouyi Yin, Eugene Tang, Paul Peng
2014	B	`conf`	Configuration approaches to improve computing efficiency of coarse-grained reconfigurable multimedia processor. FPL Chen Yang, Leibo Liu, Yansheng Wang, Shouyi Yin, Peng Cao, Shaojun Wei
2014	Misc	`conf`	Exploiting Outer Loop Parallelism of Nested Loop on Coarse-Grained Reconfigurable Architectures. FCCM Dajiang Liu, Shouyi Yin, Leibo Liu, Shaojun Wei
2014	A	`conf`	Extending lifetime of battery-powered coarse-grained reconfigurable computing platforms. DATE Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei
2014	J	`jnl`	Implementation of AVS Jizhun decoder with HW/SW partitioning on a coarse-grained reconfigurable multimedia system. Sci. China Inf. Sci. Leibo Liu, Yingjie Victor Chen, Shouyi Yin, Li Zhou, Hang Yuan, Shaojun Wei
2014	J	`jnl`	Implementation of multi-standard video decoder on a heterogeneous coarse-grained reconfigurable processor. Sci. China Inf. Sci. Leibo Liu, Yingjie Victor Chen, Dong Wang, Shouyi Yin, Xing Wang, Long Wang, Hao Lei, Peng Cao, Shaojun Wei
2014	—	`conf`	Low-power loop pipelining mapping onto CGRA utilizing variable dual VDD. MWSCAS Bing Xu, Shouyi Yin, Leibo Liu, Shaojun Wei
2014	C	`conf`	Map-reduce inspired loop parallelization on CGRA. ISCAS Shengjia Shao, Shouyi Yin, Leibo Liu, Shaojun Wei
2014	J	`jnl`	MapReduce inspired loop mapping for coarse-grained reconfigurable architecture. Sci. China Inf. Sci. Shouyi Yin, Shengjia Shao, Leibo Liu, Shaojun Wei
2014	J	`jnl`	On-Chip Memory Hierarchy in One Coarse-Grained Reconfigurable Architecture to Compress Memory Space and to Reduce Reconfiguration Time and Data-Reference Time. IEEE Trans. Very Large Scale Integr. Syst. Yansheng Wang, Leibo Liu, Shouyi Yin, Min Zhu, Peng Cao, Jun Yang, Shaojun Wei
2014	J	`jnl`	Optimization of speeded-up robust feature algorithm for hardware implementation. Sci. China Inf. Sci. Shanshan Cai, Leibo Liu, Shouyi Yin, Renyan Zhou, Weilong Zhang, Shaojun Wei
2014	J	`jnl`	Row-based configuration mechanism for a 2-D processing element array in coarse-grained reconfigurable architecture. Sci. China Inf. Sci. Leibo Liu, Yansheng Wang, Shouyi Yin, Min Zhu, Xing Wang, Shaojun Wei
2014	J	`jnl`	SimRPU: A Simulation Environment for Reconfigurable Architecture Exploration. IEEE Trans. Very Large Scale Integr. Syst. Leibo Liu, Dong Wang, Shouyi Yin, Yingjie Victor Chen, Min Zhu, Shaojun Wei
2014	C	`conf`	Teach Reconfigurable Computing using mixed-grained fabrics based hardware infrastructure. FIE Chenchen Deng, Leibo Liu, Zhaoshi Li, Shouyi Yin, Shaojun Wei
2013	J	`jnl`	A High Precision Feature Based on LBP and Gabor Theory for Face Recognition. Sensors Wei Xia, Shouyi Yin, Peng Ouyang
2013	C	`conf`	A VLSI architecture for enhancing the fault tolerance of NoC using quad-spare mesh topology and dynamic reconfiguration. ISCAS Yu Ren, Leibo Liu, Shouyi Yin, Qinghua Wu, Shaojun Wei, Jie Han
2013	J	`jnl`	A fault tolerant NoC architecture using quad-spare mesh topology and dynamic reconfiguration. J. Syst. Archit. Yu Ren, Leibo Liu, Shouyi Yin, Jie Han, Qinghua Wu, Shaojun Wei
2013	J	`jnl`	Affine Transformations for Communication and Reconfiguration Optimization of Mapping Loop Nests on CGRAs. IEICE Trans. Inf. Syst. Shouyi Yin, Dajiang Liu, Leibo Liu, Shaojun Wei
2013	C	`conf`	Affine transformations for communication and reconfiguration optimization of loops on CGRAs. ISCAS Dajiang Liu, Shouyi Yin, Leibo Liu, Shaojun Wei
2013	J	`jnl`	An Inductive-Coupling Interconnected Application-Specific 3D NoC Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Zhen Zhang, Shouyi Yin, Leibo Liu, Shaojun Wei
2013	J	`jnl`	An efficient VLSI architecture of speeded-up robust feature extraction for high resolution and high frame rate video. Sci. China Inf. Sci. Weilong Zhang, Leibo Liu, Shouyi Yin, Renyan Zhou, Shanshan Cai, Shaojun Wei
2013	—	`conf`	An energy-efficient coarse-grained dynamically reconfigurable fabric for multiple-standard video decoding applications. CICC Leibo Liu, Chenchen Deng, Dong Wang, Min Zhu, Shouyi Yin, Peng Cao, Shaojun Wei
2013	C	`conf`	An inductive-coupling interconnected application-specific 3D NoC design. ISCAS Zhen Zhang, Shouyi Yin, Leibo Liu, Shaojun Wei
2013	—	`conf`	Battery-Aware MAC Analytical Modeling for Extending Lifetime of Low Duty-Cycled Wireless Sensor Network. NAS Yulin Li, Shouyi Yin, Leibo Liu, Shaojun Wei, Dong Wang
2013	J	`jnl`	Battery-Aware Task Mapping for Coarse-Grained Reconfigurable Architecture. IEICE Trans. Inf. Syst. Shouyi Yin, Rui Shi, Leibo Liu, Shaojun Wei
2013	J	`jnl`	Calibration Techniques for Low-Power Wireless Multiband Transceiver. Int. J. Distributed Sens. Networks Shouyi Yin, Jianwei Cui, Leibo Liu, Shaojun Wei
2013	J	`jnl`	Concurrent Detection and Recognition of Individual Object Based on Colour and p-SIFT Features. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Jienan Zhang, Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei
2013	J	`jnl`	Hierarchical representation of on-chip context to reduce reconfiguration time and implementation area for coarse-grained reconfigurable architecture. Sci. China Inf. Sci. Yansheng Wang, Leibo Liu, Shouyi Yin, Min Zhu, Peng Cao, Jun Yang, Shaojun Wei
2013	C	`conf`	Implementation of multi-standard video decoding algorithms on a coarse-grained reconfigurable multimedia processor. ISCAS Leibo Liu, Yingjie Victor Chen, Shouyi Yin, Dong Wang, Xing Wang, Shaojun Wei, Li Zhou, Hao Lei, Peng Cao
2013	J	`jnl`	Low-Power Reconfigurable Processor Utilizing Variable Dual V IEEE Trans. Circuits Syst. II Express Briefs Jianfeng Zhu, Leibo Liu, Shouyi Yin, Shaojun Wei
2013	—	`conf`	Mapping IDCT of MPEG2 on Coarse-Grained Reconfigurable Array for Matching 1080p Video Decoding. EMC/HumanCom Guoyong Li, Leibo Liu, Shouyi Yin, Changkui Mao, Shaojun Wei
2013	J	`jnl`	Parallelization of Computing-Intensive Tasks of SIFT Algorithm on a Reconfigurable Architecture System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Peng Ouyang, Shouyi Yin, Hui Gao, Leibo Liu, Shaojun Wei
2013	A*	`conf`	Polyhedral model based mapping optimization of loop nests for CGRAs. DAC Dajiang Liu, Shouyi Yin, Leibo Liu, Shaojun Wei
2013	J	`jnl`	ReSSIM: a mixed-level simulator for dynamic coarse-grained reconfigurable processor. Sci. China Inf. Sci. Leibo Liu, Wen Jia, Shouyi Yin, Dong Wang, Guanyi Sun, Eugene Tang, Shaojun Wei
2013	—	`conf`	SPC: An Approach to Guarantee Performance in Cost Oriented Mapping Algorithm for NoC Architectures. NAS Qinghua Wu, Leibo Liu, Shouyi Yin, Yu Ren, Shaojun Wei
2013	—	`conf`	SURFEX: A 57fps 1080P resolution 220mW silicon implementation for simplified speeded-up robust feature with 65nm process. CICC Leibo Liu, Weilong Zhang, Chenchen Deng, Shouyi Yin, Shanshan Cai, Shaojun Wei
2013	J	`jnl`	The Organization of On-Chip Data Memory in One Coarse-Grained Reconfigurable Architecture. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yansheng Wang, Leibo Liu, Shouyi Yin, Min Zhu, Peng Cao, Jun Yang, Shaojun Wei
2012	J	`jnl`	Configuration Context Reduction for Coarse-Grained Reconfigurable Architecture. IEICE Trans. Inf. Syst. Shouyi Yin, Chongyong Yin, Leibo Liu, Min Zhu, Shaojun Wei
2012	J	`jnl`	Hybrid Wired/Wireless On-Chip Network Design for Application-Specific SoC. IEICE Trans. Electron. Shouyi Yin, Yang Hu, Zhen Zhang, Leibo Liu, Shaojun Wei
2012	J	`jnl`	Mapping Optimization of Affine Loop Nests for Reconfigurable Computing Architecture. IEICE Trans. Inf. Syst. Dajiang Liu, Shouyi Yin, Chongyong Yin, Leibo Liu, Shaojun Wei
2012	J	`jnl`	Multi-Battery Scheduling for Battery-Powered DVS Systems. IEICE Trans. Commun. Peng Ouyang, Shouyi Yin, Leibo Liu, Shaojun Wei
2012	C	`conf`	Reducing configuration contexts for coarse-grained reconfigurable architecture. ISCAS Shouyi Yin, Chongyong Yin, Leibo Liu, Min Zhu, Yansheng Wang, Shaojun Wei
2011	—	`conf`	A high efficient baseband transceiver for IEEE 802.15.4 LR-WPAN systems. ASICON Shouyi Yin, Jianwei Cui, Ao Luo, Leibo Liu, Shaojun Wei
2011	—	`conf`	Performance evaluation modeling for reconfigurable processor. ASICON Shuang Liang, Shouyi Yin, Chongyong Yin, Leibo Liu, Shaojun Wei
2010	J	`jnl`	A Cycle-Accurate Simulator for a Reconfigurable Multi-Media System. IEICE Trans. Inf. Syst. Min Zhu, Leibo Liu, Shouyi Yin, Chongyong Yin, Shaojun Wei
2010	C	`conf`	A VLSI design of sensor node for wireless image sensor network. ISCAS Renyan Zhou, Leibo Liu, Shouyi Yin, Ao Luo, Xinkai Chen, Shaojun Wei
2010	C	`conf`	A reconfigurable multi-processor SoC for media applications. ISCAS Min Zhu, Leibo Liu, Shouyi Yin, Yansheng Wang, Wenjie Wang, Shaojun Wei
2010	—	`conf`	Battery aware tasks allocating algorithm for multi-battery operated system. APCCAS Peng Ouyang, Shouyi Yin, Leibo Liu, Shaojun Wei
2010	J	`jnl`	CropNET: A Wireless Multimedia Sensor Network for Agricultural Monitoring. IEICE Trans. Commun. Shouyi Yin, Zhongfu Sun, Leibo Liu, Shaojun Wei
2010	—	`conf`	Mixed-level modeling for network on chip infrastructure in SoC design. APCCAS Yang Hu, Shouyi Yin, Leibo Liu, Shaojun Wei
2010	C	`conf`	Parallel implementation of computing-intensive decoding algorithms of H.264 on reconfigurable SoC. ISCAS Tongsheng Geng, Leibo Liu, Shouyi Yin, Min Zhu, Wen Jia, Shaojun Wei
2010	J	`jnl`	Parallelization of Computing-Intensive Tasks of the H.264 High Profile Decoding Algorithm on a Reconfigurable Multimedia System. IEICE Trans. Inf. Syst. Tongsheng Geng, Leibo Liu, Shouyi Yin, Min Zhu, Shaojun Wei
2010	—	`conf`	Syndrome differentiation of fatty liver based on the whole network analysis theory. BIBM Workshops Shouyi Yin, Tao Liu, Huafeng Wei, Guang Ji
2009	J	`jnl`	Buffer planning for application-specific networks-on-chip design. Sci. China Ser. F Inf. Sci. Shouyi Yin, Leibo Liu, Shaojun Wei
2009	J	`jnl`	Compiler Framework for Reconfigurable Computing Architecture. IEICE Trans. Electron. Chongyong Yin, Shouyi Yin, Leibo Liu, Shaojun Wei
2006	C	`conf`	Prediction-based routing for real time communications in wireless multi-hop networks. QSHINE Shouyi Yin, Yongqiang Xiong, Qian Zhang, Xiaokang Lin
2006	—	`conf`	Traffic-aware Routing for Real Time Communications in Wireless Multi-hop Networks. SUTC (1) Shouyi Yin, Yongqiang Xiong, Xiaokang Lin, Qian Zhang
2006	J	`jnl`	Traffic-aware routing for real-time communications in wireless multi-hop networks. Wirel. Commun. Mob. Comput. Shouyi Yin, Yongqiang Xiong, Qian Zhang, Xiaokang Lin
2005	B	`conf`	Adaptive load balancing in mobile ad hoc networks. WCNC Shouyi Yin, Xiaokang Lin
2005	—	`conf`	Multipath Energy Efficient Routing in Mobile Ad Hoc Network. ICN (2) Shouyi Yin, Xiaokang Lin
2005	—	`conf`	Multipath minimum energy routing in ad hoc network. ICC Shouyi Yin, Xiaokang Lin