Shounak Dhar

13 papers A* 1A 2B 1Journal 3Unranked 6
YearRankTypeTitle / Venue / Authors
2021 J jnl
DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yibo Lin, Zixuan Jiang, Jiaqi Gu, Wuxi Li, Shounak Dhar, Haoxing Ren, Brucek Khailany, David Z. Pan
2019 — conf
A shape-driven spreading algorithm using linear programming for global placement.
ASP-DAC
Shounak Dhar, Love Singhal, Mahesh A. Iyer, David Z. Pan
2019 A* conf
DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement.
DAC
Yibo Lin, Shounak Dhar, Wuxi Li, Haoxing Ren, Brucek Khailany, David Z. Pan
2019 B conf
FPGA Accelerated FPGA Placement.
FPL
Shounak Dhar, Love Singhal, Mahesh A. Iyer, David Z. Pan
2019 — conf
FPGA-Accelerated Spreading for Global Placement.
HPEC
Shounak Dhar, Love Singhal, Mahesh A. Iyer, David Z. Pan
2018 — conf
GDP: GPU accelerated Detailed Placement.
HPEC
Shounak Dhar, David Z. Pan
2018 — conf
Logic synthesis for energy-efficient photonic integrated circuits.
ASP-DAC
Zheng Zhao, Zheng Wang, Zhoufeng Ying, Shounak Dhar, Ray T. Chen, David Z. Pan
2018 J jnl
UTPlaceF 2.0: A High-Performance Clock-Aware FPGA Placement Engine.
ACM Trans. Design Autom. Electr. Syst.
Wuxi Li, Yibo Lin, Meng Li, Shounak Dhar, David Z. Pan
2018 J jnl
UTPlaceF: A Routability-Driven FPGA Placer With Physical and Congestion Aware Packing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wuxi Li, Shounak Dhar, David Z. Pan
2017 — conf
An Effective Timing-Driven Detailed Placement Algorithm for FPGAs.
ISPD
Shounak Dhar, Mahesh A. Iyer, Saurabh N. Adya, Love Singhal, Nikolay Rubanov, David Z. Pan
2017 — conf
Optical computing on silicon-on-insulator-based photonic integrated circuits.
ASICON
Zheng Zhao, Zheng Wang, Zhoufeng Ying, Shounak Dhar, Ray T. Chen, David Z. Pan
2016 A conf
Detailed placement for modern FPGAs using 2D dynamic programming.
ICCAD
Shounak Dhar, Saurabh N. Adya, Love Singhal, Mahesh A. Iyer, David Z. Pan
2016 A conf
UTPlaceF: a routability-driven FPGA placer with physical and congestion aware packing.
ICCAD
Wuxi Li, Shounak Dhar, David Z. Pan