Shota Ishihara

16 papers C 1Journal 8Unranked 7
YearRankTypeTitle / Venue / Authors
2018 — conf
A group-based scheduling method for landslide detection system with dense wireless sensor network.
ICT-DM
Shota Ishihara, Masafumi Hashimoto, Naoki Wakamiya, Masayuki Murata, Yasutaka Kawamoto
2013 J jnl
Flexible Ferroelectric-Capacitor Element for Low Power and Compact Logic-in-Memory Architectures.
J. Multiple Valued Log. Soft Comput.
Shota Ishihara, Noriaki Idobata, Masanori Hariyama, Michitaka Kameyama
2012 J jnl
Design of High-Performance Asynchronous Pipeline Using Synchronizing Logic Gates.
IEICE Trans. Electron.
Zhengfan Xia, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama
2012 C conf
Dual-rail/single-rail hybrid logic design for high-performance asynchronous circuit.
ISCAS
Zhengfan Xia, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama
2011 J jnl
A Low-Power FPGA Based on Autonomous Fine-Grain Power Gating.
IEEE Trans. Very Large Scale Integr. Syst.
Shota Ishihara, Masanori Hariyama, Michitaka Kameyama
2011 J jnl
A Switch Block for Multi-Context FPGAs Based on Floating-Gate-MOS Functional Pass-Gates Using Multiple/Binary Valued Hybrid Signals?
J. Multiple Valued Log. Soft Comput.
Shota Ishihara, Noriaki Idobata, Yoshihiro Nakatani, Masanori Hariyama
2011 — conf
An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture.
ASP-DAC
Yoshiya Komatsu, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama
2011 J jnl
Implementation of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture.
IEICE Trans. Electron.
Shota Ishihara, Ryoto Tsuchiya, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama
2010 J jnl
A Switch Block Architecture for Multi-Context FPGAs Based on a Ferroelectric-Capacitor Functional Pass-Gate Using Multiple/Binary Valued Hybrid Signals.
IEICE Trans. Inf. Syst.
Shota Ishihara, Noriaki Idobata, Masanori Hariyama, Michitaka Kameyama
2010 J jnl
An Asynchronous FPGA Based on LEDR/4-Phase-Dual-Rail Hybrid Architecture.
IEICE Trans. Electron.
Shota Ishihara, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama
2010 — conf
An Field-Programmable VLSI Based on Synchronous/Asynchronous Hybrid Architecture.
ERSA
Masanori Hariyama, Ryoto Tsuchiya, Shota Ishihara, Michitaka Kameyama
2009 — conf
A Fine-Grain SIMD Architecture Based on Flexible Ferroelectric-Capacitor Logic.
ERSA
Shota Ishihara, Noriaki Idobata, Masanori Hariyama, Michitaka Kameyama
2009 — conf
A low-power FPGA based on autonomous fine-grain power-gating.
ASP-DAC
Shota Ishihara, Masanori Hariyama, Michitaka Kameyama
2009 — conf
An Asynchronous Field-Programmable VLSI Using LEDR/4-Phase-Dual-Rail Protocol Converters.
ERSA
Shota Ishihara, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama
2008 J jnl
Evaluation of a Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture.
IEICE Trans. Electron.
Masanori Hariyama, Shota Ishihara, Michitaka Kameyama
2008 — conf
Non-Volatile Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals.
ERSA
Masanori Hariyama, Shota Ishihara, Noriaki Idobata, Michitaka Kameyama