Shorin Kyo

20 papers A* 1A 1Misc 3Journal 9Unranked 6
YearRankTypeTitle / Venue / Authors
2013 — conf
AutoPilot: message passing parallel programming for a cache incoherent embedded manycore processor.
MES
Ben Kelly, William B. Gardner, Shorin Kyo
2012 Misc conf
Efficient data transfer operations for a SIMD processor array system.
ICASSP
Hanno Lieske, Shorin Kyo, Shouhei Nomoto, Sunao Torii, Yuki Kobayashi, Yasuyuki Ninomiya, Shin'ichiro Okazaki
2011 — conf
A dynamic SIMD/MIMD mode switching processor for embedded real-time image recognition systems.
A-SSCC
Shouhei Nomoto, Shorin Kyo, Shin'ichiro Okazaki
2011 J jnl
Guest Editorial: Special Issue on Computing Architectures for Real-Time Video/Image Analysis.
J. Signal Process. Syst.
Shao-Yi Chien, Shorin Kyo, Tsung-Han Tsai
2011 J jnl
IMAPCAR: A 100 GOPS In-Vehicle Vision Processor Based on 128 Ring Connected Four-Way VLIW Processing Elements.
J. Signal Process. Syst.
Shorin Kyo, Shin'ichiro Okazaki
2010 J jnl
Performance Evaluation of a Dynamically Switchable SIMD/MIMD Processor by Using an Image Recognition Application.
Inf. Media Technol.
Shouhei Nomoto, Shorin Kyo, Shin'ichiro Okazaki
2010 J jnl
Performance Evaluation of a Dynamically Switchable SIMD/MIMD Processor by Using an Image Recognition Application.
IPSJ Trans. Syst. LSI Des. Methodol.
Shouhei Nomoto, Shorin Kyo, Shin'ichiro Okazaki
2009 — conf
IMAPCAR2: A dynamic SIMD/MIMD mode switching processor for embedded systems.
Hot Chips Symposium
Shorin Kyo, Shouhei Nomoto, Takuya Koga, Hanno Lieske, Shin'ichiro Okazaki
2009 — conf
Mapping schemes of image recognition tasks onto highly parallel SIMD/MIMD processors.
ICDSC
Shorin Kyo, Shouhei Nomoto, Shin'ichiro Okazaki
2008 — conf
In-vehicle vision processors for driver assistance systems.
ASP-DAC
Shorin Kyo, Shin'ichiro Okazaki
2008 J jnl
Overtaking Vehicle Detection Method and Its Implementation Using IMAPCAR Highly Parallel Image Processor.
IEICE Trans. Inf. Syst.
Kazuyuki Sakurai, Shorin Kyo, Shin'ichiro Okazaki
2007 A conf
A low-cost mixed-mode parallel processor architecture for embedded systems.
ICS
Shorin Kyo, Takuya Koga, Hanno Lieske, Shouhei Nomoto, Shin'ichiro Okazaki
2007 J jnl
An Integrated Memory Array Processor for Embedded Image Recognition Systems.
IEEE Trans. Computers
Shorin Kyo, Shin'ichiro Okazaki, Tamio Arai
2007 J jnl
Media Processing LSI Architectures for Automotives - Challenges and Future Trends - .
IEICE Trans. Electron.
Ichiro Kuroda, Shorin Kyo
2007 Misc conf
Overtaking Vehicle Detection Method and Its Implementation Using IMAPCAR Highly Parallel Image Processor.
MVA
Kazuyuki Sakurai, Shorin Kyo, Shin'ichiro Okazaki
2005 A* conf
An Integrated Memory Array Processor Architecture for Embedded Image Recognition Systems.
ISCA
Shorin Kyo, Shin'ichiro Okazaki, Tamio Arai
2004 J jnl
A 51.2 GOPS Programmable Video Recognition Processor for Vision-Based Intelligent Cruise Control Applications.
IEICE Trans. Inf. Syst.
Shorin Kyo, Takuya Koga, Shin'ichiro Okazaki, Ichiro Kuroda
2003 J jnl
A 51.2-GOPS scalable video recognition processor for intelligent cruise control based on a linear array of 128 four-way VLIW processing elements.
IEEE J. Solid State Circuits
Shorin Kyo, Takuya Koga, Shin'ichiro Okazaki, Ichiro Kuroda
2002 Misc conf
A 51.2GOPS Programmable Video Recognition Processor for Vision Based Intelligent Cruise Control Applications.
MVA
Shorin Kyo
2001 — conf
IMAP-CE: a 51.2 GOPS video rate image processor with 128 VLIW processing elements.
ICIP (3)
Shorin Kyo, Takuya Koga, Shin'ichiro Okazaki