Shoji Otaka

22 papers C 1Journal 13Unranked 8
YearRankTypeTitle / Venue / Authors
2022 J jnl
Sub-GHz Two-Way Ranging Based on Phase Detection for Remote Keyless Entry Systems.
IEEE Trans. Veh. Technol.
Ichiro Seto, Shoji Otaka, Hiroshi Yoshida, Katsuya Nonin, Masaki Nishikawa, Takayuki Kato, Yoshiharu Nito, Hideyuki Ishiwata, Tomoaki Ohtsuki
2020 — conf
Sub-GHz Phase-Based Ranging System: Implementation and Evaluation.
VTC Spring
Masayoshi Oshiro, Shoji Otaka, Takayuki Kato, Katsuya Nonin, Masaki Nishikawa, Yoshiharu Nito, Hideyuki Ishiwata, Hiroshi Yoshida
2018 J jnl
A 1024-QAM Capable WLAN Receiver with -56.3dB Image Rejection Ratio Using Self-Calibration Technique.
IEICE Trans. Electron.
Shusuke Kawai, Toshiyuki Yamagishi, Yosuke Hagiwara, Shigehito Saigusa, Ichiro Seto, Shoji Otaka, Shuichi Ito
2017 C conf
A 1024-QAM capable WLAN receiver with -56.3 dB image rejection ratio using self-calibration technique.
ISCAS
Shusuke Kawai, Toshiyuki Yamagishi, Yosuke Hagiwara, Shigehito Saigusa, Ichiro Seto, Shoji Otaka, Shuichi Ito
2013 — conf
A 1.8GHz linear CMOS power amplifier with supply-path switching scheme for WCDMA/LTE applications.
ISSCC
Kohei Onizuka, Shigehito Saigusa, Shoji Otaka
2012 — conf
A +30.5 dBm CMOS Doherty power amplifier with reliability enhancement technique.
VLSIC
Kohei Onizuka, Shigehito Saigusa, Shoji Otaka
2012 J jnl
A 1.9 GHz CMOS Power Amplifier With Embedded Linearizer to Compensate AM-PM Distortion.
IEEE J. Solid State Circuits
Kohei Onizuka, Hiroaki Ishihara, Masahiro Hosoya, Shigehito Saigusa, Osamu Watanabe, Shoji Otaka
2011 — conf
A 1.5GHz-modulation-range 10ms-modulation-period 180kHzrms-frequency-error 26MHz-reference mixed-mode FMCW synthesizer for mm-wave radar application.
ISSCC
Hiroki Sakurai, Yuka Kobayashi, Toshiya Mitomo, Osamu Watanabe, Shoji Otaka
2011 — conf
A 1.9/2.4GHz dual band CMOS power amplifier with integrated AM-PM distortion canceller.
CICC
Kohei Onizuka, Hiroaki Ishihara, Masahiro Hosoya, Shigehito Saigusa, Osamu Watanabe, Shoji Otaka
2010 J jnl
A 10-MHz Signal Bandwidth Cartesian Loop Transmitter Capable of Off-Chip PA Linearization.
IEEE J. Solid State Circuits
Hiroaki Ishihara, Masahiro Hosoya, Shoji Otaka, Osamu Watanabe
2010 — conf
A 10MHz signal bandwidth Cartesian-loop transmitter capable of off-chip PA linearization.
ISSCC
Hiroaki Ishihara, Masahiro Hosoya, Shoji Otaka, Osamu Watanabe
2008 — conf
0.13 μm CMOS Cartesian loop transmitter IC with fast calibration and switching scheme from opened to closed loop.
ESSCIRC
Shoji Otaka, Masahiro Hosoya, Hiroaki Ishihara, Toru Hashimoto, Yuta Araki
2007 — conf
ECO chip: Energy Consumption Zeroize Chip with a 953MHz High-Sensitivity Radio Wave Detector for Standby Mode Applications.
CICC
Toshiyuki Umeda, Shoji Otaka
2006 J jnl
A 950-MHz rectifier circuit for sensor network tags with 10-m distance.
IEEE J. Solid State Circuits
Toshiyuki Umeda, Hiroshi Yoshida, Shuichi Sekine, Yumi Fujita, Takuji Suzuki, Shoji Otaka
2005 J jnl
A Low LO Leakage and Low Power LO Buffer for Direct-Conversion Quadrature Demodulator.
IEICE Trans. Electron.
Toshiya Mitomo, Osamu Watanabe, Shoji Otaka, Ryuichi Fujimoto, Shunji Kawaguchi
2004 J jnl
A +10-dBm IIP
IEEE J. Solid State Circuits
Shoji Otaka, Mitsuyuki Ashida, Masato Ishii, Tetsuro Itakura
2003 J jnl
A 1-V 2-GHz CMOS Up-Converter Using Self-Switching Mixers.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Toshiyuki Umeda, Shoji Otaka, Kenji Kojima, Tetsuro Itakura
2002 J jnl
A 7-GHz 1.8-dB NF CMOS low-noise amplifier.
IEEE J. Solid State Circuits
Ryuichi Fujimoto, Kenji Kojima, Shoji Otaka
2000 J jnl
A low-power low-noise accurate linear-in-dB variable-gain amplifier with 500-MHz bandwidth.
IEEE J. Solid State Circuits
Shoji Otaka, Gaku Takemura, Hiroshi Tanimoto
1997 J jnl
A 1.9-GHz Si-bipolar variable attenuator for PHS transmitter.
IEEE J. Solid State Circuits
Shoji Otaka, Hiroshi Tanimoto, Shuji Watanabe, Tadahiko Maeda
1996 J jnl
A low local input 1.9 GHz Si-bipolar quadrature modulator with no adjustment.
IEEE J. Solid State Circuits
Shoji Otaka, Takafumi Yamaji, Ryuichi Fujimoto, Chikau Takahashi, Hiroshi Tanimoto
1992 J jnl
High-speed CMOS I/O buffer circuits.
IEEE J. Solid State Circuits
Manabu Ishibe, Shoji Otaka, Junichi Takeda, Shigeru Tanaka, Yoshiaki Toyoshima, Satoru Takatsuka, Shoichi Shimizu