Shobha Vasudevan

63 papers A* 8A 15B 1C 2Misc 7Journal 18Unranked 12

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	BAMBI integrates biostatistical and artificial intelligence methods to improve RNA biomarker discovery. Briefings Bioinform. Peng Zhou, Zixiu Li, Feifan Liu, Euijin Kwon, Tien-Chan Hsieh, Shangyuan Ye, Shobha Vasudevan, Jung Ae Lee, Khanh-Van Tran, Chan Zhou
2025	A	`conf`	Towards Foundation Database Models. CIDR Johannes Wehrstein, Carsten Binnig, Fatma Özcan, Shobha Vasudevan, Yu Gan, Yawen Wang
2024	J	`jnl`	ARISTOTLE: Feature Engineering for Scalable Application-Level Post-Silicon Debugging. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Debjit Pal, Shobha Vasudevan
2021	J	`jnl`	Feature Engineering for Scalable Application-Level Post-Silicon Debugging. CoRR Debjit Pal, Shobha Vasudevan
2021	A*	`conf`	Learning Semantic Representations to Verify Hardware Designs. NeurIPS Shobha Vasudevan, Wenjie Jiang, David Bieber, Rishabh Singh, Hamid Shojaei, Richard Ho, Charles Sutton
2020	J	`jnl`	Assertion Ranking Using RTL Source Code Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Debjit Pal, Spencer Offenberger, Shobha Vasudevan
2020	J	`jnl`	Emphasizing Functional Relevance Over State Restoration in Post-Silicon Signal Tracing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Debjit Pal, Sai Ma, Shobha Vasudevan
2019	—	`conf`	A figure of merit for assertions in verification. ASP-DAC Samuel Hertz, Debjit Pal, Spencer Offenberger, Shobha Vasudevan
2019	A	`conf`	Guilty As Charged: Computational Reliability Threats Posed By Electrostatic Discharge-induced Soft Errors. DATE Keven Feng, Sandeep Vora, Rui Jiang, Elyse Rosenbaum, Shobha Vasudevan
2018	A*	`conf`	Application level hardware tracing for scaling post-silicon debug. DAC Debjit Pal, Abhishek Sharma, Sandip Ray, Flavio M. de Paula, Shobha Vasudevan
2018	—	`conf`	Automated Generation and Selection of Interpretable Features for Enterprise Security. IEEE BigData Jiayi Duan, Ziheng Zeng, Alina Oprea, Shobha Vasudevan
2017	J	`jnl`	A novel test compression algorithm for analog circuits to decrease production costs. Integr. Seyed Nematollah Ahmadyan, Suriyaprakash Natarajan, Shobha Vasudevan
2017	—	`conf`	Still a Fight to Get It Right: Verification in the Era of Machine Learning. ICRC Shobha Vasudevan
2016	J	`jnl`	Automated Transient Input Stimuli Generation for Analog Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Seyed Nematollah Adel Ahmadyan, Shobha Vasudevan
2016	A	`conf`	Duplex: simultaneous parameter-performance exploration for optimizing analog circuits. ICCAD Seyed Nematollah Ahmadyan, Shobha Vasudevan
2016	—	`conf`	Every test makes a difference: Compressing analog tests to decrease production costs. ASP-DAC Seyed Nematollah Ahmadyan, Suriyaprakash Natarajan, Shobha Vasudevan
2016	Misc	`conf`	Symptomatic Bug Localization for Functional Debug of Hardware Designs. VLSID Debjit Pal, Shobha Vasudevan
2015	A	`conf`	Can't See the Forest for the Trees: State Restoration's Limitations in Post-silicon Trace Signal Selection. ICCAD Sai Ma, Debjit Pal, Rui Jiang, Sandip Ray, Shobha Vasudevan
2015	A	`conf`	Fast eye diagram analysis for high-speed CMOS circuits. DATE Seyed Nematollah Ahmadyan, Chenjie Gu, Suriyaprakash Natarajan, Eli Chiprout, Shobha Vasudevan
2015	—	`conf`	Packer classifier based on PE header information. HotSoS Qiao Jin, Jiayi Duan, Shobha Vasudevan, Michael D. Bailey
2014	Misc	`conf`	A Coverage Guided Mining Approach for Automatic Generation of Succinct Assertions. VLSID David Sheridan, Lingyi Liu, Hyungsul Kim, Shobha Vasudevan
2014	A*	`conf`	Code Coverage of Assertions Using RTL Source Code Analysis. DAC Viraj Athavale, Sai Ma, Samuel Hertz, Shobha Vasudevan
2014	J	`jnl`	Efficient Statistical Model Checking of Hardware Circuits With Multiple Failure Regions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jayanand Asok Kumar, Seyed Nematollah Ahmadyan, Shobha Vasudevan
2014	J	`jnl`	Scaling Input Stimulus Generation through Hybrid Static and Dynamic Analysis of RTL. ACM Trans. Design Autom. Electr. Syst. Lingyi Liu, Shobha Vasudevan
2013	J	`jnl`	Automatic Generation of System Level Assertions from Transaction Level Models. J. Electron. Test. Lingyi Liu, Shobha Vasudevan
2013	A	`conf`	Diagnosing root causes of system level performance violations. ICCAD Lingyi Liu, Xuanyu Zhong, Xiaotao Chen, Shobha Vasudevan
2013	J	`jnl`	Formal Probabilistic Timing Verification in RTL. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jayanand Asok Kumar, Shobha Vasudevan
2013	—	`conf`	Generating concise assertions with complete coverage. ACM Great Lakes Symposium on VLSI Chen-Hsuan Lin, Lingyi Liu, Shobha Vasudevan
2013	J	`jnl`	Mining Hardware Assertions With Guidance From Static Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Samuel Hertz, David Sheridan, Shobha Vasudevan
2013	A	`conf`	Reachability analysis of nonlinear analog circuits through iterative reachable set reduction. DATE Seyed Nematollah Ahmadyan, Shobha Vasudevan
2013	A	`conf`	Runtime verification of nonlinear analog circuits using incremental time-augmented RRT algorithm. DATE Seyed Nematollah Ahmadyan, Jayanand Asok Kumar, Shobha Vasudevan
2013	—	`conf`	Scaling RTL property checking using feasible path analysisand decomposition. ACM Great Lakes Symposium on VLSI Lingyi Liu, Shobha Vasudevan
2013	A*	`conf`	Using automatically generated invariants for regression testing and bug localization. ASE Parth Sagdeo, Nicholas Ewalt, Debjit Pal, Shobha Vasudevan
2012	J	`jnl`	A Technique for Test Coverage Closure Using GoldMine. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lingyi Liu, David Sheridan, William Tuohy, Shobha Vasudevan
2012	A*	`conf`	Early prediction of NBTI effects using RTL source code analysis. DAC Jayanand Asok Kumar, Kenneth M. Butler, Heesoo Kim, Shobha Vasudevan
2012	J	`jnl`	Formal Performance Analysis for Faulty MIMO Hardware. IEEE Trans. Very Large Scale Integr. Syst. Jayanand Asok Kumar, Shobha Vasudevan
2012	A*	`conf`	Goal-oriented stimulus generation for analog circuits. DAC Seyed Nematollah Ahmadyan, Jayanand Asok Kumar, Shobha Vasudevan
2012	Misc	`conf`	Using static analysis for coverage extraction fromemulation/prototyping platforms. CODES+ISSS Viraj Athavale, Sam Hertz, Darshan Jetly, Vijay Ganesan, Jim Krysl, Shobha Vasudevan
2012	—	`conf`	Verifying dynamic power management schemes using statistical model checking. ASP-DAC Jayanand Asok Kumar, Shobha Vasudevan
2012	A	`conf`	Word level feature discovery to enhance quality of assertion mining. ICCAD Lingyi Liu, Chen-Hsuan Lin, Shobha Vasudevan
2011	C	`conf`	Automatic generation of assertions from system level design using data mining. MEMOCODE Lingyi Liu, David Sheridan, Viraj Athavale, Shobha Vasudevan
2011	Misc	`conf`	Coverage closure in SoC verification: Are we chasing a mirage? VTS Shobha Vasudevan
2011	A	`conf`	Efficient validation input generation in RTL by hybridized source code analysis. DATE Lingyi Liu, Shobha Vasudevan
2011	A*	`conf`	PRECIS: Inferring invariants using program path guided clustering. ASE Parth Sagdeo, Viraj Athavale, Sumant Kowshik, Shobha Vasudevan
2011	B	`conf`	Scaling probabilistic timing verification of hardware using abstractions in design source code. FMCAD Jayanand Asok Kumar, Lingyi Liu, Shobha Vasudevan
2011	A*	`conf`	Signature Pattern Covering via Local Greedy Algorithm and Pattern Shrink. ICDM Hyungsul Kim, Sungjin Im, Tarek F. Abdelzaher, Jiawei Han, David Sheridan, Shobha Vasudevan
2011	A	`conf`	Towards coverage closure: Using GoldMine assertions for generating design validation stimulus. DATE Lingyi Liu, David Sheridan, William Tuohy, Shobha Vasudevan
2011	Misc	`conf`	Variation-Conscious Formal Timing Verification in RTL. VLSI Design Jayanand Asok Kumar, Shobha Vasudevan
2010	—	`conf`	Automatic Compositional Reasoning for Probabilistic Model Checking of Hardware Designs. QEST Jayanand Asok Kumar, Shobha Vasudevan
2010	A	`conf`	GoldMine: Automatic assertion generation using data mining and static analysis. DATE Shobha Vasudevan, David Sheridan, Sanjay J. Patel, David Tcheng, William Tuohy, Daniel R. Johnson
2010	A	`conf`	Statistical guarantees of performance for MIMO designs. DSN Jayanand Asok Kumar, Shobha Vasudevan
2009	Misc	`conf`	Dedicated Rewriting: Automatic Verification of Low Power Transformations in RTL. VLSI Design Vinod Viswanath, Shobha Vasudevan, Jacob A. Abraham
2009	J	`jnl`	Dedicated Rewriting: Automatic Verification of Low Power Transformations in Register Transfer Level. J. Low Power Electron. Vinod Viswanath, Shobha Vasudevan, Jacob A. Abraham
2009	—	`conf`	STAR: Generating input vectors for design validation by static analysis of RTL. HLDVT Lingyi Liu, Shobha Vasudevan
2008	J	`jnl`	Sequential equivalence checking between system level and RTL descriptions. Des. Autom. Embed. Syst. Shobha Vasudevan, Vinod Viswanath, Jacob A. Abraham, Jiajin Tu
2007	J	`jnl`	Automatic Verification of Arithmetic Circuits in RTL Using Stepwise Refinement of Term Rewriting Systems. IEEE Trans. Computers Shobha Vasudevan, Vinod Viswanath, Robert W. Sumners, Jacob A. Abraham
2007	Misc	`conf`	Efficient Microprocessor Verification using Antecedent Conditioned Slicing. VLSI Design Shobha Vasudevan, Vinod Viswanath, Jacob A. Abraham
2007	J	`jnl`	Improved verification of hardware designs through antecedent conditioned slicing. Int. J. Softw. Tools Technol. Transf. Shobha Vasudevan, E. Allen Emerson, Jacob A. Abraham
2006	C	`conf`	Automatic decomposition for sequential equivalence checking of system level and RTL descriptions. MEMOCODE Shobha Vasudevan, Jacob A. Abraham, Vinod Viswanath, Jiajin Tu
2006	A	`conf`	Automatic generation of instruction sequences targeting hard-to-detect structural faults in a processor. ITC Sankar Gurumurthy, Shobha Vasudevan, Jacob A. Abraham
2005	A	`conf`	Automated mapping of pre-computed module-level test sequences to processor instructions. ITC S. Guramurthy, Shobha Vasudevan, Jacob A. Abraham
2004	—	`conf`	Efficient Model Checking of Hardware Using Conditioned Slicing. AVoCS Shobha Vasudevan, E. Allen Emerson, Jacob A. Abraham
2004	—	`conf`	Static program transformations for efficient software model checking. IFIP Congress Topical Sessions Shobha Vasudevan, Jacob A. Abraham