Sho Ikeda - RankMe

14 papers A* 1C 1Journal 3Unranked 9

Year	Rank	Type	Title / Venue / Authors
2024	A*	`conf`	Hierarchical Light Sampling with Accurate Spherical Gaussian Lighting. SIGGRAPH Asia Yusuke Tokuyoshi, Sho Ikeda, Paritosh Kulkarni, Takahiro Harada
2022	—	`conf`	Fused BVH to Ray Trace Level of Detail Meshes. SIGGRAPH Asia Posters Paritosh Kulkarni, Sho Ikeda, Takahiro Harada
2017	J	`jnl`	A - 244-dB FOM High-Frequency Piezoelectric Resonator-Based Cascaded Fractional-N PLL With Sub-ppb-Order Channel-Adjusting Technique. IEEE J. Solid State Circuits Sho Ikeda, Hiroyuki Ito, Akifumi Kasamatsu, Yosuke Ishikawa, Takayoshi Obara, Naoki Noguchi, Koji Kamisuki, Yao Jiyang, Shinsuke Hara, Ruibing Dong, Shiro Dosho, Noboru Ishihara, Kazuya Masu
2017	—	`conf`	Design of high-frequency piezoelectric resonator-based cascaded fractional-N PLL with sub-ppb-order channel adjusting technique. ASP-DAC Yosuke Ishikawa, Sho Ikeda, Hiroyuki Ito, Akifumi Kasamatsu, Takayoshi Obara, Naoki Noguchi, Koji Kamisuki, Yao Jiyang, Shinsuke Hara, Ruibing Dong, Shiro Dosho, Noboru Ishihara, Kazuya Masu
2016	—	`conf`	An 8.865-GHz -244dB-FOM high-frequency piezoelectric resonator-based cascaded fractional-N PLL with sub-ppb-order channel adjusting technique. VLSI Circuits Sho Ikeda, Hiroyuki Ito, Akifumi Kasamatsu, Yosuke Ishikawa, Takayoshi Obara, Naoki Noguchi, Koji Kamisuki, Yao Jiyang, Shinsuke Hara, Ruibing Dong, Shiro Dosho, Noboru Ishihara, Kazuya Masu
2015	C	`conf`	A 0.5-V 1.56-mW 5.5-GHz RF transceiver IC module with J-shaped folded monopole antenna. ISCAS Yosuke Ishikawa, Sang-yeop Lee, Shin Yonezawa, Sho Ikeda, Yiming Fang, Taisuke Hamada, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu
2015	—	`conf`	A 0.5-V 5.8-GHz low-power asymmetrical QPSK/OOK transceiver for wireless sensor network. ASP-DAC Sho Ikeda, Sang-yeop Lee, Shin Yonezawa, Yiming Fang, Motohiro Takayasu, Taisuke Hamada, Yosuke Ishikawa, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu
2014	—	`conf`	A 0.52-V 5.7-GHz low noise sub-sampling PLL with dynamic threshold MOSFET. A-SSCC Sho Ikeda, Sang-yeop Lee, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu
2014	—	`conf`	A 950μW 5.5-GHz low voltage PLL with digitally-calibrated ILFD and linearized varactor. ASP-DAC Sho Ikeda, Tatsuya Kamimura, Sang-yeop Lee, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu
2014	J	`jnl`	A Sub-1mW Class-C-VCO-Based Low Voltage PLL with Ultra-Low-Power Digitally-Calibrated ILFD in 65nm CMOS. IEICE Trans. Electron. Sho Ikeda, Sang-yeop Lee, Tatsuya Kamimura, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu
2013	—	`conf`	Performance Improvement of Physically Based Spectral Rendering Using Stochastic Sampling. CCIW Shin Watanabe, Shota Kanamori, Sho Ikeda, Bisser Raytchev, Toru Tamaki, Kazufumi Kaneda
2012	J	`jnl`	A Ring-VCO-Based Injection-Locked Frequency Multiplier with Novel Pulse Generation Technique in 65 nm CMOS. IEICE Trans. Electron. Sang-yeop Lee, Norifumi Kanemaru, Sho Ikeda, Tatsuya Kamimura, Satoru Tanoi, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu
2012	—	`conf`	Optimal design method for chip-area-efficient CMOS low-dropout regulator. APCCAS Sho Ikeda, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu
2011	—	`conf`	A ring-VCO-based injection-locked frequency multiplier using a new pulse generation technique in 65 nm CMOS. ISOCC Norifumi Kanemaru, Sho Ikeda, Tatsuya Kamimura, Sang-yeop Lee, Satoru Tanoi, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu