Shmuel Wimer

47 papers A* 2C 2Journal 40Unranked 3
YearRankTypeTitle / Venue / Authors
2023 J jnl
A Self-Refreshable Bit-Cell for Single-Cycle Refreshing of Embedded Memories.
IEEE Trans. Computers
Binyamin Frankel, Shmuel Wimer
2023 J jnl
Energy Efficiency of Opportunistic Refreshing for Gain-Cell Embedded DRAM.
IEEE Trans. Circuits Syst. I Regul. Pap.
Binyamin Frankel, Eyal Sarfati, Davide Rossi, Shmuel Wimer
2021 J jnl
Resource allocation in rooted trees subject to sum constraints and nonlinear cost functions.
Inf. Process. Lett.
Nir Halman, Shmuel Wimer
2018 J jnl
Accurate Shielded Interconnect Delay Estimation by Reconfigurable Ring Oscillator.
IEEE Trans. Circuits Syst. I Regul. Pap.
Eyal Sarfati, Binyamin Frankel, Yitzhak Birk, Shmuel Wimer
2018 J jnl
Optimal queuing-based memory refreshing algorithm for energy efficient processors.
Comput. Electr. Eng.
Roi Herman, Binyamin Frankel, Shmuel Wimer
2018 J jnl
Queuing-Based eDRAM Refreshing for Ultra-Low Power Processors.
IEEE Trans. Computers
Binyamin Frankel, Roi Herman, Shmuel Wimer
2017 J jnl
Optimal VLSI Delay Tuning by Space Tapering With Clock-Tree Application.
IEEE Trans. Circuits Syst. I Regul. Pap.
Eyal Sarfati, Binyamin Frankel, Yitzhak Birk, Shmuel Wimer
2017 J jnl
Probability-Driven Multibit Flip-Flop Integration With Clock Gating.
IEEE Trans. Very Large Scale Integr. Syst.
Doron Gluzer, Shmuel Wimer
2016 J jnl
Energy efficient computing by multi-mode addition.
Integr.
Amir Albeck, Shmuel Wimer
2016 — conf
Energy efficient deeply fused dot-product multiplication architecture.
ASAP
Shmuel Wimer, Israel Koren
2016 J jnl
Opportunistic Refreshing Algorithm for eDRAM Memories.
IEEE Trans. Circuits Syst. I Regul. Pap.
Amit Kazimirsky, Shmuel Wimer
2016 J jnl
Optimal VLSI Delay Tuning by Wire Shielding.
J. Optim. Theory Appl.
Binyamin Frankel, Shmuel Wimer
2016 J jnl
Optimal weight allocation in rooted trees.
J. Comb. Optim.
Shmuel Wimer
2015 J jnl
Energy efficient hybrid adder architecture.
Integr.
Shmuel Wimer, Amnon Stanislavsky
2015 J jnl
Mixing Drivers in Clock-Tree for Power Supply Noise Reduction.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yakov Kaplan, Shmuel Wimer
2015 J jnl
Timing-constrained power minimization in VLSI circuits by simultaneous multilayer wire spacing.
Integr.
Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny
2014 J jnl
A Look-Ahead Clock Gating Based on Auto-Gated Flip-Flops.
IEEE Trans. Circuits Syst. I Regul. Pap.
Shmuel Wimer, Arye Albahari
2014 J jnl
A Low Energy and High Performance ${\rm DM}^{2}$ Adder.
IEEE Trans. Circuits Syst. I Regul. Pap.
Itamar Levi, Amir Albeck, Alexander Fish, Shmuel Wimer
2014 J jnl
A low energy dual-mode adder.
Comput. Electr. Eng.
Shmuel Wimer, Amir Albeck, Israel Koren
2014 J jnl
Cell-based interconnect migration by hierarchical optimization.
Integr.
Eugene Shaphir, Ron Y. Pinter, Shmuel Wimer
2014 J jnl
Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating.
IEEE Trans. Very Large Scale Integr. Syst.
Shmuel Wimer, Israel Koren
2014 J jnl
Easy and difficult exact covering problems arising in VLSI power reduction by clock gating.
Discret. Optim.
Shmuel Wimer
2014 J jnl
Planar CMOS to multi-gate layout conversion for maximal fin utilization.
Integr.
Shmuel Wimer
2014 J jnl
Using well-solvable minimum cost exact covering for VLSI clock energy minimization.
Oper. Res. Lett.
Shmuel Wimer, Doron Gluzer, Uri Wimer
2013 J jnl
On optimal flip-flop grouping for VLSI power minimization.
Oper. Res. Lett.
Shmuel Wimer
2012 J jnl
The Optimal Fan-Out of Clock Network for Power Minimization by Adaptive Gating.
IEEE Trans. Very Large Scale Integr. Syst.
Shmuel Wimer, Israel Koren
2012 J jnl
The complexity of VLSI power-delay optimization by interconnect resizing.
J. Comb. Optim.
Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer
2012 J jnl
Using well-solvable quadratic assignment problems for VLSI interconnect applications.
Discret. Appl. Math.
Ben Emanuel, Shmuel Wimer, Gershon Wolansky
2011 C conf
A Cost Effective Centralized Adaptive Routing for Networks-on-Chip.
DSD
Ran Manevich, Israel Cidon, Avinoam Kolodny, Isask'har Walter, Shmuel Wimer
2011 J jnl
The Wiener maximum quadratic assignment problem.
Discret. Optim.
Eranda Çela, Nina S. Schmuck, Shmuel Wimer, Gerhard J. Woeginger
2010 J jnl
Interconnect Bundle Sizing Under Discrete Design Rules.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer
2010 — conf
Interconnect power and delay optimization by dynamic programming in gridded design rules.
ISPD
Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer
2009 J jnl
Power-delay optimization in VLSI microprocessors by wire spacing.
ACM Trans. Design Autom. Electr. Syst.
Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer
2008 J jnl
On optimal ordering of signals in parallel wire bundles.
Integr.
Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny
2008 J jnl
Timing-aware power-optimal ordering of signals.
ACM Trans. Design Autom. Electr. Syst.
Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer
2006 J jnl
Optimal bus sizing in migration of processor design.
IEEE Trans. Circuits Syst. I Regul. Pap.
Shmuel Wimer, Shay Michaely, Konstantin Moiseev, Avinoam Kolodny
2006 C conf
Timing optimization of interconnect by simultaneous net-ordering, wire sizing and spacing.
ISCAS
Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny
2004 — conf
Optimal resizing of bus wires in layout migration.
ICECS
Shay Michaely, Shmuel Wimer, Avinoam Kolodny
1993 J jnl
An efficient algorithm for some multirow layout problems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jack A. Feldman, Israel A. Wagner, Shmuel Wimer
1993 J jnl
On Paths with the Shortest Average Arc Length in Weighted Graphs.
Discret. Appl. Math.
Shmuel Wimer, Israel Koren, Israel Cederbaum
1992 J jnl
Balanced Block Spacing for VLSI Layout.
Discret. Appl. Math.
Israel Cederbaum, Israel Koren, Shmuel Wimer
1989 J jnl
Depth-first-search and dynamic programming algorithms for efficient CMOS cell generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Reuven Bar-Yehuda, Jack A. Feldman, Ron Y. Pinter, Shmuel Wimer
1989 J jnl
Optimal aspect ratios of building blocks in VLSI.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shmuel Wimer, Israel Koren, Israel Cederbaum
1988 J jnl
Analysis of strategies for constructive general block placement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shmuel Wimer, Israel Koren
1988 A* conf
Optimal Aspect Ratios of Building Blocks in VLSI.
DAC
Shmuel Wimer, Israel Koren, Israel Cederbaum
1987 J jnl
Optimal Chaining of CMOS Transistors in a Functional Cell.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shmuel Wimer, Ron Y. Pinter, Jack A. Feldman
1983 A* conf
HOPLA-PLA optimization and synthesis.
DAC
Shmuel Wimer, N. Sharfman