Shlomo Weiss

65 papers A* 9A 2B 2Misc 1Journal 44Unranked 7
YearRankTypeTitle / Venue / Authors
2021 J jnl
A novel low power hybrid cache using GC-EDRAM cells.
Integr.
Junyi Zhou, Roger Kahn, Shlomo Weiss
2020 J jnl
Perceptron based filtering of futile prefetches in embedded VLIW DSPs.
J. Syst. Archit.
David Uzan, Roger Kahn, Shlomo Weiss
2018 J jnl
Decoupled Branch Predictor for Embedded DSP.
IEEE Embed. Syst. Lett.
Konstantin Berestizshevsky, Shlomo Weiss
2018 J jnl
SiMT-DSP: A Massively Multithreaded DSP Architecture.
IEEE Trans. Very Large Scale Integr. Syst.
Ben Perach, Shlomo Weiss
2016 J jnl
An NoC Simulator That Supports Deflection Routing, GPU/CPU Integration, and Co-Simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Gadi Oxman, Shlomo Weiss
2016 J jnl
Deflection Routing in Hierarchical Mesh NoCs.
IEEE Embed. Syst. Lett.
Gadi Oxman, Shlomo Weiss
2015 B conf
DNOC: an accurate and fast virtual channel and deflection routing network-on-chip simulator.
ISPASS
Gadi Oxman, Shlomo Weiss
2014 J jnl
Computational methods for Conway's Game of Life cellular automaton.
J. Comput. Sci.
Gadi Oxman, Shlomo Weiss, Yair Be'ery
2014 J jnl
Fast evaluation of a time-domain non-linear cochlear model on GPUs.
J. Comput. Phys.
Doron Sabo, Oded Barzelay, Shlomo Weiss, Miriam Furst
2014 J jnl
L1-L2 Interconnect Design Methodology and Arbitration in 3-D IC Multicore Compute Clusters.
IEEE Trans. Very Large Scale Integr. Syst.
Alexei Jolondz, Shlomo Weiss, Amit Golander
2014 J jnl
Protein Sequence Pattern Matching: Leveraging Application Specific Hardware Accelerators.
IEEE Trans. Computers
Sagi Manole, Amit Golander, Shlomo Weiss
2014 J jnl
RIDER: Ring deflection router with buffers.
Des. Autom. Embed. Syst.
Gadi Oxman, Shlomo Weiss
2013 Misc conf
A Parallel Algorithm for a Physiological Non-Linear Model of the Cochlea.
ICCS
Doron Sabo, Shlomo Weiss, Miriam Furst
2013 J jnl
Low-latency adaptive mode transitions and hierarchical power management in asymmetric clustered cores.
ACM Trans. Archit. Code Optim.
Eran Shifer, Shlomo Weiss
2013 J jnl
Phase-change memory: An architectural perspective.
ACM Comput. Surv.
Omer Zilberberg, Shlomo Weiss, Sivan Toledo
2012 J jnl
Architectural virtualization extensions: A systems perspective.
Comput. Sci. Rev.
Simon Grinberg, Shlomo Weiss
2012 — conf
Buffered deflection routing for networks-on-chip.
INA-OCMC@HiPEAC
Gadi Oxman, Shlomo Weiss, Yitzhak (Tsahi) Birk
2012 J jnl
Complex Floating Point - A Novel Data Word Representation for DSP Processors.
IEEE Trans. Circuits Syst. I Regul. Pap.
Nadav Cohen, Shlomo Weiss
2012 — conf
Streamlined Network-on-Chip for Multicore Embedded Architectures.
ARCS
Gadi Oxman, Shlomo Weiss, Yitzhak (Tsahi) Birk
2012 J jnl
Virtio network paravirtualization driver: Implementation and performance of a de-facto standard.
Comput. Stand. Interfaces
Gal Motika, Shlomo Weiss
2010 J jnl
Branch target buffer design for embedded processors.
Microprocess. Microsystems
Nadav Levison, Shlomo Weiss
2010 A conf
Low power branch prediction for embedded application processors.
ISLPED
Nadav Levison, Shlomo Weiss
2010 J jnl
Reducing leakage power with BTB access prediction.
Integr.
Roger Kahn, Shlomo Weiss
2009 J jnl
Checkpoint allocation and release.
ACM Trans. Archit. Code Optim.
Amit Golander, Shlomo Weiss
2009 J jnl
Reexecution and Selective Reuse in Checkpoint Processors.
Trans. High Perform. Embed. Archit. Compil.
Amit Golander, Shlomo Weiss
2009 J jnl
Service level agreement for multithreaded processors.
ACM Trans. Archit. Code Optim.
Ron Gabor, Avi Mendelson, Shlomo Weiss
2009 J jnl
Synchronizing Redundant Cores in a Dynamic DMR Multicore Architecture.
IEEE Trans. Circuits Syst. II Express Briefs
Amit Golander, Shlomo Weiss, Ronny Ronen
2008 J jnl
DDMR: Dynamic and Scalable Dual Modular Redundancy with Short Validation Intervals.
IEEE Comput. Archit. Lett.
Amit Golander, Shlomo Weiss, Ronny Ronen
2008 J jnl
Hiding the misprediction penalty of a resource-efficient high-performance processor.
ACM Trans. Archit. Code Optim.
Amit Golander, Shlomo Weiss
2008 J jnl
Thrifty BTB: A comprehensive solution for dynamic power reduction in branch target buffers.
Microprocess. Microsystems
Roger Kahn, Shlomo Weiss
2007 J jnl
Fairness enforcement in switch on event multithreading.
ACM Trans. Archit. Code Optim.
Ron Gabor, Shlomo Weiss, Avi Mendelson
2006 A* conf
Fairness and Throughput in Switch on Event Multithreading.
MICRO
Ron Gabor, Shlomo Weiss, Avi Mendelson
2006 J jnl
Power-aware out-of-order issue logic in high-performance microprocessors.
Microprocess. Microsystems
Yehuda Sadeh Weinraub, Shlomo Weiss
2004 J jnl
Programming Windows NT device drivers to operate non-interrupting embedded devices.
Microprocess. Microsystems
Tomer Karin, Shlomo Weiss
2004 — conf
Selective main memory compression by identifying program phase changes.
WMPI
Doron Nakar, Shlomo Weiss
2003 J jnl
Approximate prefix coding for system-on-a-chip programs.
J. Syst. Archit.
Shlomo Weiss, Roman Tsikel
2003 J jnl
Class-Based Decompressor Design for Compressed Instruction Memory in Embedded Processors.
IEEE Trans. Computers
Shlomo Weiss, Shay Beren
2003 J jnl
Embedded instruction memory in automotive engine controllers.
IEEE Trans. Veh. Technol.
Tal Oved, Shlomo Weiss
2003 B conf
Pattern Matching by means of Multi-Resolution Compression.
DCC
Avishay Orpaz, Shlomo Weiss
2002 J jnl
A PCI bus simulation framework and some simulation results on PCI standard 2.1 latency limitations.
J. Syst. Archit.
Ehud Finkelstein, Shlomo Weiss
2002 — conf
A study of CodePack: optimizing embedded code space.
CODES
Avishay Orpaz, Shlomo Weiss
2001 — conf
HW/SW partitioning of an embedded instruction memory decompressor.
CODES
Shlomo Weiss, Shay Beren
1999 J jnl
Extending PCI Performance Beyond the Desktop.
Computer
Shlomo Weiss, Ehud Finkelstein
1999 J jnl
Microprocessor system buses: A case study.
J. Syst. Archit.
Ehud Finkelstein, Shlomo Weiss
1998 A* conf
Branch Prediction Based on Universal Data Compression Algorithms.
ISCA
Eitan Federovsky, Meir Feder, Shlomo Weiss
1998 J jnl
Floating point micropipeline performance.
J. Syst. Archit.
Shlomo Weiss, A. Goldstein
1998 J jnl
Implementation and Analysis of Path History in Dynamic Branch Prediction Schemes.
IEEE Trans. Computers
Shlomo Reches, Shlomo Weiss
1997 A conf
Implementation and Analysis of Path History in Dynamic Branch Prediction Schemes.
International Conference on Supercomputing
Shlomo Reches, Shlomo Weiss
1995 A* conf
Implementing Register Interlocks in Parallel-Pipeline Multiple Instruction Queue, Superscalar Processors.
HPCA
Shlomo Weiss
1994 J jnl
PowerPC 601 and Alpha 21064: A Tale of Two RISCs.
Computer
James E. Smith, Shlomo Weiss
1993 J jnl
Optimizing a superscalar machine to run vector code.
IEEE Parallel Distributed Technol. Syst. Appl.
Shlomo Weiss
1992 J jnl
Memory conflict resolution in vector supercomputers.
J. Supercomput.
Shlomo Weiss
1992 J jnl
Scalar Memory References in Pipelined Multiprocessors: A Performance Study.
IEEE Trans. Software Eng.
Ravi Ganesan, Shlomo Weiss
1991 — conf
Multiple-Port Memory Access in Decoupled Architecture Processors.
ICPP (1)
Shlomo Weiss
1990 J jnl
A study of scalar compilation techniques for pipelined supercomputers.
ACM Trans. Math. Softw.
Shlomo Weiss, James E. Smith
1989 A* conf
An Aperiodic Storage Scheme to Reduce Memory Conflicts in Vector Processors.
ISCA
Shlomo Weiss
1989 J jnl
Scalar supercomputer architecture.
Proc. IEEE
Shlomo Weiss
1987 A* conf
A Study of Scalar Compilation Techniques for Pipelined Supercomputers.
ASPLOS
Shlomo Weiss, James E. Smith
1986 J jnl
A Simulation Study of Decoupled Architecture Computers.
IEEE Trans. Computers
James E. Smith, Shlomo Weiss, Nicholas Y. Pang
1986 A* conf
DOSS: a storage system for design data.
DAC
Shlomo Weiss, Katie Rotzell, Tom Rhyne, Arny Goldfein
1984 A* conf
Design transaction management.
DAC
Randy H. Katz, Shlomo Weiss
1984 A* conf
Instruction Issue Logic for Pipelined Supercomputers.
ISCA
Shlomo Weiss, James E. Smith
1984 J jnl
Instruction Issue Logic in Pipelined Supercomputers.
IEEE Trans. Computers
Shlomo Weiss, James E. Smith
1984 — conf
Recovery of In-Memory Data Structures for Interactive Update Applications.
COMPCON
Shlomo Weiss
1983 A* conf
Chip assemblers: Concepts and capabilities.
DAC
Randy H. Katz, Shlomo Weiss