Shiyu Su - RankMe

37 papers A* 3A 3Journal 13Unranked 18

Year	Rank	Type	Title / Venue / Authors
2026	A*	`conf`	A PN-Free Digital 3-SAT Accelerator Using Crossbar Architecture and Frequency-Controlled Counters. HPCA Zhezheng Ren, Chenao Yuan, Yuke Zhang, Shiyu Su
2025	—	`conf`	11.2 A Blocker-Tolerant Receiver with VCO-Based Non-Uniform Multi-Level Time-Approximation Filter with -36dB EVM in 28nm CMOS. ISSCC Ce Yang, Shiyu Su, Mostafa M. Ayesh, Soumya Mahapatra, Maysara M. Hamada, Vinay Chenna, Hossein Hashemi, Mike Shuo-Wei Chen
2025	—	`conf`	26.1: A 24GHz Direct Digital Transmitter Using Multiphase Subharmonic Switching PA Achieving 3.2Gb/s Data Rate and -30.8dB EVM in 65nm CMOS. ISSCC Soumya Mahapatra, Mostafa M. Ayesh, Ce Yang, Mayank Palaria, Shiyu Su, Aoyang Zhang, Mike Shuo-Wei Chen
2025	J	`jnl`	A Blocker-Tolerant Receiver With VCO-Based Non-Uniform Multi-Level Time-Approximation Filter. IEEE J. Solid State Circuits Ce Yang, Shiyu Su, Mostafa M. Ayesh, Soumya Mahapatra, Maysara Hamada, Vinay Chenna, Hossein Hashemi, Mike Shuo-Wei Chen
2025	J	`jnl`	A Millimeter-Wave Direct Digital Transmitter Using Multiphase Subharmonic Switching PA. IEEE J. Solid State Circuits Soumya Mahapatra, Mostafa M. Ayesh, Ce Yang, Mayank Palaria, Shiyu Su, Aoyang Zhang, Mike Shuo-Wei Chen
2025	J	`jnl`	Stochastic TDC Using Common-Mode Time Dithering and Passive Approximate Adders. IEEE J. Solid State Circuits Shiyu Su, Qiaochu Zhang, Baishakhi Rani Biswas, Sandeep K. Gupta, Mike Shuo-Wei Chen
2024	—	`conf`	A Stochastic Analog SAT Solver in 65nm CMOS Achieving 6.6μs Average Solution Time with 100% Solvability for Hard 3-SAT Problems. VLSI Technology and Circuits Qiaochu Zhang, Shiyu Su, Zerui Liu, Hsiang-Chun Cheng, Zhengyi Qiu, Mayank Palaria, Jiacheng Ye, Deming Meng, Buyun Chen, Sushmit Hossain, Wei Wu, Mike Shuo-Wei Chen
2024	J	`jnl`	Fractional-N Digital MDLL With Injection-Error Scrambling and Calibration. IEEE J. Solid State Circuits Qiaochu Zhang, Hsiang-Chun Cheng, Shiyu Su, Mike Shuo-Wei Chen
2024	—	`conf`	Synthesizable 10-bit Stochastic TDC Using Common-Mode Time Dithering and Passive Approximate Adder with 0.012mm VLSI Technology and Circuits Qiaochu Zhang, Shiyu Su, Baishakhi Rani Biswas, Sandeep Gupta, Mike Shuo-Wei Chen
2023	—	`conf`	A 2GS/s 8.5-Bit Time-Based ADC using a Segmented Stochastic Flash TDC. CICC Shiyu Su, Qiaochu Zhang, Mike Shuo-Wei Chen
2023	—	`conf`	A Fractional-N Digital MDLL with Injection-Error Scrambling and Background Third-Order DTC Delay Equalizer Achieving -67dBc Fractional Spur. ISSCC Qiaochu Zhang, Hsiang-Chun Cheng, Shiyu Su, Mike Shuo-Wei Chen
2023	—	`conf`	A Memristor-Based Analog Accelerator for Solving Quadratic Programming Problems. CICC Hsiang-Chun Cheng, Shiyu Su, Mayank Palaria, Qiaochu Zhang, Ce Yang, Sushmit Hossain, Ryan M. Bena, Buyun Chen, Zerui Liu, Juzheng Liu, Rezwan A. Rasul, Quan Nguyen, Wei Wu, Mike Shuo-Wei Chen
2023	—	`conf`	Analog Kalman Filter with Integration and Digitization via a Shared Thyristor-Based VCO for Sensor Fusion in 65 nm CMOS. ESSCIRC Mayank Palaria, Shiyu Su, Hsiang-Chun Cheng, Rezwan A. Rasul, Qiaochu Zhang, Soumya Mahapatra, Chong-Fatt Law, Sushmit Hossain, Ryan M. Bena, Wei Wu, Quan Nguyen, Mike Shuo-Wei Chen
2023	J	`jnl`	Millimeter-Wave Receiver With Non-Uniform Time-Approximation Filter. IEEE J. Solid State Circuits Ce Yang, Shiyu Su, Mike Shuo-Wei Chen
2022	J	`jnl`	A Fractional-N Digital MDLL With Background Two-Point DTC Calibration. IEEE J. Solid State Circuits Qiaochu Zhang, Shiyu Su, Cheng-Ru Ho, Mike Shuo-Wei Chen
2022	A*	`conf`	A cost-efficient fully synthesizable stochastic time-to-digital converter design based on integral nonlinearity scrambling. DAC Qiaochu Zhang, Shiyu Su, Mike Shuo-Wei Chen
2022	—	`conf`	Analog/Mixed-Signal Circuit Synthesis Enabled by the Advancements of Circuit Architectures and Machine Learning Algorithms. ASP-DAC Shiyu Su, Qiaochu Zhang, Mohsen Hassanpourghadi, Juzheng Liu, Rezwan A. Rasul, Mike Shuo-Wei Chen
2022	—	`conf`	High-Speed Digital-to-Analog Converter Design Towards High Dynamic Range. CICC Shiyu Su, Mike Shuo-Wei Chen
2022	J	`jnl`	SAW-Less Direct RF Transmitter With Multimode Noise Shaping and Tri-Level Time-Approximation Filter. IEEE J. Solid State Circuits Shiyu Su, Mike Shuo-Wei Chen
2022	—	`conf`	TAFA: Design Automation of Analog Mixed-Signal FIR Filters Using Time Approximation Architecture. ASP-DAC Shiyu Su, Qiaochu Zhang, Juzheng Liu, Mohsen Hassanpourghadi, Rezwan A. Rasul, Mike Shuo-Wei Chen
2021	—	`conf`	29.4 A Fractional-N Digital MDLL with Background Two-Point DTC Calibration Achieving -60dBc Fractional Spur. ISSCC Qiaochu Zhang, Shiyu Su, Cheng-Ru Ho, Mike Shuo-Wei Chen
2021	J	`jnl`	A Time-Approximation Filter for Direct RF Transmitter. IEEE J. Solid State Circuits Shiyu Su, Mike Shuo-Wei Chen
2021	J	`jnl`	Analog/Mixed-Signal Circuit Synthesis Enabled by the Advancements of Circuit Architectures and Machine Learning Algorithms. CoRR Shiyu Su, Qiaochu Zhang, Mohsen Hassanpourghadi, Juzheng Liu, Rezwan A. Rasul, Mike Shuo-Wei Chen
2021	A*	`conf`	Circuit Connectivity Inspired Neural Network for Analog Mixed-Signal Functional Modeling. DAC Mohsen Hassanpourghadi, Shiyu Su, Rezwan A. Rasul, Juzheng Liu, Qiaochu Zhang, Mike Shuo-Wei Chen
2021	A	`conf`	From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer Learning. ICCAD Juzheng Liu, Shiyu Su, Meghna Madhusudan, Mohsen Hassanpourghadi, Samuel Saunders, Qiaochu Zhang, Rezwan A. Rasul, Yaguang Li, Jiang Hu, Arvind Kumar Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Anthony Levi, Sandeep Gupta, Mike Shuo-Wei Chen
2021	J	`jnl`	TAFA: Design Automation of Analog Mixed-Signal FIR Filters Using Time Approximation Architecture. CoRR Shiyu Su, Qiaochu Zhang, Juzheng Liu, Mohsen Hassanpourghadi, Rezwan A. Rasul, Mike Shuo-Wei Chen
2020	—	`conf`	10.2 A SAW-Less Direct-Digital RF Modulator with Tri-Level Time-Approximation Filter and Reconfigurable Dual-Band Delta-Sigma Modulation. ISSCC Shiyu Su, Mike Shuo-Wei Chen
2020	A	`conf`	CEPA: CNN-based Early Performance Assertion Scheme for Analog and Mixed-Signal Circuit Simulation. ICCAD Qiaochu Zhang, Shiyu Su, Juzheng Liu, Mike Shuo-Wei Chen
2020	—	`conf`	Millimeter-Wave Communications with Beamforming for UAV-Assisted Railway Monitoring System. IoTaaS Shiyu Su
2020	A	`conf`	Transfer Learning with Bayesian Optimization-Aided Sampling for Efficient AMS Circuit Modeling. ICCAD Juzheng Liu, Mohsen Hassanpourghadi, Qiaochu Zhang, Shiyu Su, Mike Shuo-Wei Chen
2019	—	`conf`	A 1-5GHz Direct-Digital RF Modulator with an Embedded Time-Approximation Filter Achieving -43dB EVM at 1024 QAM. VLSI Circuits Shiyu Su, Mike Shuo-Wei Chen
2018	J	`jnl`	A 16-bit 12-GS/s Single-/Dual-Rate DAC With a Successive Bandpass Delta-Sigma Modulator Achieving <-67-dBc IM3 Within DC to 6-GHz Tunable Passbands. IEEE J. Solid State Circuits Shiyu Su, Mike Shuo-Wei Chen
2018	—	`conf`	A 16b 12GS/S single/dual-rate DAC with successive bandpass delta-sigma modulator achieving <-67dBc IM3 within DC-to-6GHz tunable passbands. ISSCC Shiyu Su, Mike Shuo-Wei Chen
2016	—	`conf`	27.1 A 12b 2GS/s dual-rate hybrid DAC with pulsed timing-error pre-distortion and in-band noise Cancellation Achieving >74dBc SFDR up to 1GHz in 65nm CMOS. ISSCC Shiyu Su, Mike Shuo-Wei Chen
2016	J	`jnl`	A 12-Bit 2 GS/s Dual-Rate Hybrid DAC With Pulse-Error Pre-Distortion and In-Band Noise Cancellation Achieving > 74 dBc SFDR and <-80 dBc IM3 up to 1 GHz in 65 nm CMOS. IEEE J. Solid State Circuits Shiyu Su, Mike Shuo-Wei Chen
2015	J	`jnl`	A 12 bit 1 GS/s Dual-Rate Hybrid DAC With an 8 GS/s Unrolled Pipeline Delta-Sigma Modulator Achieving > 75 dB SFDR Over the Nyquist Band. IEEE J. Solid State Circuits Shiyu Su, Tu-I Tsai, Praveen Kumar Sharma, Mike Shuo-Wei Chen
2014	—	`conf`	A 12-bit hybrid DAC with 8GS/s unrolled pipeline delta-sigma modulator achieving >75dB SFDR over 500MHz in 65nm CMOS. VLSIC Shiyu Su, Tu-I Tsai, Praveen Kumar Sharma, Mike Shuo-Wei Chen