Shivendra Singh Parihar

13 papers A* 1A 1C 1Journal 5Unranked 5
YearRankTypeTitle / Venue / Authors
2026 J jnl
Evaluation of Radiation Resilience, Performance, and V
IEEE Trans. Computers
Hafeez Raza, Mahdi Benkhelifa, Koshal Kumar, Shivendra Singh Parihar, Yogesh Singh Chauhan, Hussam Amrouch, Avinash Lahgere
2025 C conf
Benchmarking Cryogenic Circuits using 5 nm FinFETs for Quantum Processing.
ISCAS
Anirban Kar, Shivendra Singh Parihar, Florian Klemme, Yogesh Singh Chauhan, Hussam Amrouch
2025 J jnl
Cryo-CACTI: Cryogenic-Aware CACTI for Cache Modeling Down to 10K in Advanced 7nm FinFETs.
IEEE Trans. Computers
Divya Praneetha Ravipati, Victor M. van Santen, Shivendra Singh Parihar, Yogesh Singh Chauhan, Preeti Ranjan Panda, Hussam Amrouch
2025 A conf
Pushing the Boundaries of AI Chips: From Monolithic 3D CMOS to Cryogenic Computing.
DATE
Mahdi Benkhelifa, Shivendra Singh Parihar, Anirban Kar, Girish Pahwa, Yogesh Singh Chauhan, Hussam Amrouch
2024 J jnl
Energy-Efficient Cryogenic Ternary Content Addressable Memory using Ferroelectric SQUID.
CoRR
Shamiul Alam, Simon Thomann, Shivendra Singh Parihar, Yogesh Singh Chauhan, Kai Ni, Hussam Amrouch, Ahmedullah Aziz
2024 — conf
Impact of Self-Heating in 5nm FinFETs at Cryogenic Temperatures for Reliable Quantum Computing: Device-Circuit Interaction.
IRPS
Shivendra Singh Parihar, Girish Pahwa, Yogesh Singh Chauhan, Hussam Amrouch
2024 — conf
Technology Mapping for Cryogenic CMOS Circuits.
ISVLSI
Benjamin Hien, Marcel Walter, Victor M. van Santen, Florian Klemme, Shivendra Singh Parihar, Girish Pahwa, Yogesh Singh Chauhan, Hussam Amrouch, Robert Wille
2023 — conf
5nm FinFET Cryogenic SRAM Evaluation for Quantum Computing.
DRC
Shivendra Singh Parihar, Simon Thomann, Girish Pahwa, Yogesh Singh Chauhan, Hussam Amrouch
2023 J jnl
Cryogenic CMOS for Quantum Processing: 5-nm FinFET-Based SRAM Arrays at 10 K.
IEEE Trans. Circuits Syst. I Regul. Pap.
Shivendra Singh Parihar, Victor M. van Santen, Simon Thomann, Girish Pahwa, Yogesh Singh Chauhan, Hussam Amrouch
2023 J jnl
Cryogenic In-Memory Computing for Quantum Processors Using Commercial 5-nm FinFETs.
IEEE Open J. Circuits Syst.
Shivendra Singh Parihar, Simon Thomann, Girish Pahwa, Yogesh Singh Chauhan, Hussam Amrouch
2023 A* conf
Design Automation for Cryogenic CMOS Circuits.
DAC
Victor M. van Santen, Marcel Walter, Florian Klemme, Shivendra Singh Parihar, Girish Pahwa, Yogesh Singh Chauhan, Robert Wille, Hussam Amrouch
2022 — conf
Self-Heating characterization and modeling of 5nm technology node FinFETs.
DRC
Shivendra Singh Parihar, Jun Z. Huang, Weike Wang, Kimihiko Imura, Yogesh Singh Chauhan
2019 — conf
Compact Modeling of Drain-Extended MOS Transistor Using BSIM-BULK Model.
VDAT
Shivendra Singh Parihar, Ramchandra Gurjar