Shirshendu Das

54 papers A 3C 1Misc 7Journal 23Unranked 20

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Exploiting virtual channel allocation policies in STT-RAM buffers of NoC routers through hardware Trojan. J. Syst. Archit. Josna Philomina, Rekha K. James, Palash Das, Shirshendu Das, Daleesha M. Viswanathan
2026	J	`jnl`	NeSTAR: Hardware Trojans and its mitigation strategy in NoC routers. Integr. Josna Philomina, Rekha K. James, Shirshendu Das, Palash Das, Daleesha M. Viswanathan
2025	—	`conf`	$\mathcal{RRR}$: Rethinking Randomized Remapping for High Performance Secured NVM LLC. HOST Prathamesh Nitin Tanksale, Guru Raghava S. Seethiraju, Shirshendu Das, Venkata Kalyan Tavva
2025	J	`jnl`	SmartDeCoup: Decoupling the STT-RAM LLC for even write distribution and lifetime improvement. J. Syst. Archit. Prabuddha Sinha, Krishna Prathik B. V., Shirshendu Das, Venkata Kalyan Tavva
2025	J	`jnl`	TENDRA: Targeted Endurance Attack on STT-RAM LLC. IEEE Embed. Syst. Lett. Prabuddha Sinha, Mangena Likhit Sai, Shirshendu Das, Venkata Kalyan Tavva
2024	A	`conf`	$\mathcal{F}lush+early\mathcal{R}\text{ELOAD}$: Covert Channels Attack on Shared LLC Using MSHR Merging. DATE Aditya S. Gangwar, Prathamesh Nitin Tanksale, Shirshendu Das, Sudeepta Mishra
2024	J	`jnl`	HTree: Hardware Trojan Attack on Cache Resizing Policies. IEEE Embed. Syst. Lett. Atul Kumar, Shirshendu Das, Basant Subba
2024	—	`conf`	LiveWay: Dynamic Write Bypassing for Lifetime Enhancement in STT-RAM LLC. HIPCW Prabuddha Sinha, Krishna Prathik B. V., Shirshendu Das, Venkata Kalyan Tavva
2024	—	`conf`	PROLONG: Priority based Write Bypassing Technique for Longer Lifetime in STT-RAM based LLC. MEMSYS Prabuddha Sinha, Krishna Pratik B. V., Shirshendu Das, Venkata Kalyan Tavva
2024	J	`jnl`	RSPP: Restricted Static Pseudo-Partitioning for Mitigation of Cross-Core Covert Channel Attacks. ACM Trans. Design Autom. Electr. Syst. Jaspinder Kaur, Shirshendu Das
2023	—	`conf`	ACPC: Covert Channel Attack on Last Level Cache using Dynamic Cache Partitioning. ISQED Jaspinder Kaur, Shirshendu Das
2023	J	`jnl`	TPPD: Targeted Pseudo Partitioning based Defence for cross-core covert channel attacks. J. Syst. Archit. Jaspinder Kaur, Shirshendu Das
2023	J	`jnl`	Variation aware power management for GPU memories. Microprocess. Microsystems Divyansh Maura, Tanmay Goel, Kaustav Goswami, Dip Sankar Banerjee, Shirshendu Das
2023	J	`jnl`	edAttack: Hardware Trojan Attack on On-Chip Packet Compression. IEEE Des. Test Atul Kumar, Dipika Deb, Shirshendu Das, Palash Das
2022	—	`conf`	A Case for Amplifying Row Hammer Attacks via Cell-Coupling in DRAM Devices. MEMSYS Kaustav Goswami, Shirshendu Das, Sagar Satapathy, Dip Sankar Banerjee
2022	J	`jnl`	BHT-NoC: Blaming Hardware Trojans in NoC Routers. IEEE Des. Test Bharat Bisht, Shirshendu Das
2022	—	`conf`	Hybrid Refresh: Improving DRAM Performance by Handling Weak Rows Smartly. MEMSYS Samiksha Verma, Shirshendu Das, Vipul Bondre
2022	—	`conf`	PV-aware Replacement Policy for Two-level Shared Cache. iSES Bindu Agarwalla, Nilkanta Sahu, Shirshendu Das
2022	J	`jnl`	Process variation aware DRAM-Cache resizing. J. Syst. Archit. Bindu Agarwalla, Shirshendu Das, Nilkanta Sahu
2022	J	`jnl`	TPPD: Targeted Pseudo Partitioning based Defence for Cross-Core Covert Channel Attacks. CoRR Jaspinder Kaur, Shirshendu Das
2022	J	`jnl`	VAR-DRAM: Variation-Aware Framework for Efficient Dynamic Random Access Memory Design. CoRR Kaustav Goswami, Hemanta Kumar Mondal, Shirshendu Das, Dip Sankar Banerjee
2022	J	`jnl`	WinDRAM: Weak rows as in-DRAM cache. Concurr. Comput. Pract. Exp. Sudershan Kumar, Prabuddha Sinha, Shirshendu Das
2021	A	`conf`	A Fairness Conscious Cache Replacement Policy for Last Level Cache. DATE Kousik Kumar Dutta, Prathamesh Nitin Tanksale, Shirshendu Das
2021	J	`jnl`	A Survey on Cache Timing Channel Attacks for Multicore Processors. J. Hardw. Syst. Secur. Jaspinder Kaur, Shirshendu Das
2021	J	`jnl`	Efficient Cache Resizing policy for DRAM-based LLCs in ChipMultiprocessors. J. Syst. Archit. Bindu Agarwalla, Shirshendu Das, Nilkanta Sahu
2021	—	`conf`	Efficient On-chip Communication for Neuromorphic Systems. SmartWorld/SCALCOM/UIC/ATC/IOP/SCI Shobhit Kumar, Shirshendu Das, Manaal Mukhtar Jamadar, Jaspinder Kaur
2021	A	`conf`	Exploiting Secrets by Leveraging Dynamic Cache Partitioning of Last Level Cache. DATE Anurag Agarwal, Jaspinder Kaur, Shirshendu Das
2021	—	`conf`	MAPCP: Memory Access Pattern Classifying Prefetcher. MEMSYS Manaal Mukhtar Jamadar, Jaspinder Kaur, Shirshendu Das
2021	J	`jnl`	Towards Enhanced System Efficiency while Mitigating Row Hammer. ACM Trans. Archit. Code Optim. Kaustav Goswami, Dip Sankar Banerjee, Shirshendu Das
2021	—	`conf`	Towards Row Sensitive DRAM Refresh through Retention Awareness. ISQED Tanmay Goel, Divyansh Maura, Kaustav Goswami, Shirshendu Das, Dip Sankar Banerjee
2019	J	`jnl`	Cost effective routing techniques in 2D mesh NoC using on-chip transmission lines. J. Parallel Distributed Comput. Dipika Deb, John Jose, Shirshendu Das, Hemangee K. Kapoor
2019	—	`conf`	State Preserving Dynamic DRAM Bank Re-Configurations for Enhanced Power Efficiency. ISQED Kaustav Goswami, Hemanta Kumar Mondal, Shirshendu Das, Dip Sankar Banerjee
2018	Misc	`conf`	Dynamic Thermal Management by Using Task Migration in Conjunction with Frequency Scaling for Chip Multiprocessors. VLSID Alankar V. Umdekar, Arijit Nath, Shirshendu Das, Hemangee K. Kapoor
2017	J	`jnl`	Dynamic Associativity Management in Tiled CMPs by Runtime Adaptation of Fellow Sets. IEEE Trans. Parallel Distributed Syst. Shirshendu Das, Hemangee K. Kapoor
2017	—	`conf`	Latency Aware Block Replacement for L1 Caches in Chip Multiprocessor. ISVLSI Shirshendu Das, Hemangee K. Kapoor
2016	J	`jnl`	A Framework for Block Placement, Migration, and Fast Searching in Tiled-DNUCA Architecture. ACM Trans. Design Autom. Electr. Syst. Shirshendu Das, Hemangee K. Kapoor
2016	Misc	`conf`	Dynamic associativity enabled DNUCA to improve block localisation in tiled CMPs. SAC Shirshendu Das, Hemangee K. Kapoor
2016	Misc	`conf`	Static energy efficient cache reconfiguration for dynamic NUCA in tiled CMPs. SAC Shounak Chakraborty, Shirshendu Das, Hemangee K. Kapoor
2016	—	`conf`	Tag only storage for capacity optimised last level cache in chip multiprocessors. VDAT Surajit Das, Shirshendu Das, Hemangee K. Kapoor
2016	Misc	`conf`	Towards a Better Cache Utilization by Selective Data Storage for CMP Last Level Caches. VLSID Shirshendu Das, Hemangee K. Kapoor
2015	—	`conf`	An efficient searching mechanism for dynamic NUCA in chip multiprocessors. VDAT Kartheek Vanapalli, Hemangee K. Kapoor, Shirshendu Das
2015	Misc	`conf`	Dynamic associativity management using utility based way-sharing. SAC Shirshendu Das, Hemangee K. Kapoor
2015	Misc	`conf`	Exploration of Migration and Replacement Policies for Dynamic NUCA over Tiled CMPs. VLSID Shirshendu Das, Hemangee K. Kapoor
2015	—	`conf`	Performance Constrained Static Energy Reduction Using Way-Sharing Target-Banks. IPDPS Workshops Shounak Chakraborty, Shirshendu Das, Hemangee K. Kapoor
2015	—	`conf`	Power aware cache miss reduction by energy efficient victim retention. VDAT Shounak Chakraborty, Shirshendu Das, Hemangee K. Kapoor
2015	Misc	`conf`	Static energy reduction by performance linked cache capacity management in tiled CMPs. SAC Hemangee K. Kapoor, Shirshendu Das, Shounak Chakraborty
2014	—	`conf`	An Approach for Multicast Routing in Networks-on-Chip. ICIT M. Lakshmi Prasad, Shirshendu Das, Hemangee K. Kapoor
2014	—	`conf`	RT-DVS for Power Optimization in Multiprocessor Real-Time Systems. ICIT B. Venkateswarlu Naik, Shirshendu Das, Hemangee K. Kapoor
2014	J	`jnl`	Victim retention for reducing cache misses in tiled chip multiprocessors. Microprocess. Microsystems Shirshendu Das, Hemangee K. Kapoor
2013	J	`jnl`	A formal framework for interfacing mixed-timing systems. Integr. Shirshendu Das, Parasara Sridhar Duggirala, Hemangee K. Kapoor
2013	J	`jnl`	Design and formal verification of a hierarchical cache coherence protocol for NoC based multiprocessors. J. Supercomput. Hemangee K. Kapoor, Praveen Kanakala, Malti Verma, Shirshendu Das
2013	—	`conf`	Dynamic Associativity Management Using Fellow Sets. ISED Shirshendu Das, Hemangee K. Kapoor
2013	—	`conf`	Random-LRU: A Replacement Policy for Chip Multiprocessors. VDAT Shirshendu Das, Nagaraju Polavarapu, Prateek D. Halwe, Hemangee K. Kapoor
2013	C	`conf`	Towards a Better Cache Utilization Using Controlled Cache Partitioning. DASC Prateek D. Halwe, Shirshendu Das, Hemangee K. Kapoor